Sample-and-Hold Clock Phase Alignment Across Mixed-Voltage ADC Circuits
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional A/D converters face accuracy issues due to inappropriate clock timing in sample and hold circuits, which affects the operation accuracy and reliability, especially when dealing with different electrical withstand voltages between input and output signals.
Innovation Solution
A semiconductor integrated circuit with a sample and hold circuit and a clock generation circuit that includes devices with different withstand voltages, where the clock generation circuit adjusts the phase of the second clock signal to match the phase of the first clock signal using a delay adjustment circuit, ensuring accurate sampling and holding across varying voltage domains.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If devices with different withstand voltages are used in the sample and hold circuit to handle different voltage domains, then the adaptability to different electrical withstand voltages is improved, but the clock timing synchronization between circuits becomes more difficult to maintain
Solution Approach 1:
A delay adjustment circuit is introduced as an intermediary component between the first clock signal source and the second clock signal source. This circuit adjusts the timing of the second clock signal to compensate for timing differences caused by different device characteristics, thereby maintaining synchronization without requiring the clock sources to be directly coupled.
Solution Approach 2:
The delay adjustment circuit performs preliminary timing adjustment on the second clock signal before it is used to control switches in the sample and hold circuit. This advance adjustment ensures that clock timing is synchronized before the actual sampling operation begins, preventing timing errors during conversion.
2Measurement precision
If the clock timing in the sample and hold circuit is optimized for high accuracy, then the operation accuracy is improved, but the circuit complexity increases due to additional delay adjustment mechanisms
Solution Approach 1:
The delay adjustment circuit modifies the timing parameter of the second clock signal by adjusting its phase or delay amount. This parameter change allows precise control over clock timing to match the first clock signal, achieving high operation accuracy without requiring complex circuit reconfiguration.
3Reliability
If devices with higher withstand voltage are used to handle input signals, then the electrical tolerance is improved, but the operation speed may be reduced compared to lower withstand voltage devices
Solution Approach 1:
Different devices with appropriate withstand voltage ratings are assigned to different parts of the circuit based on local requirements. High withstand voltage devices are used where voltage tolerance is critical, while lower withstand voltage devices with faster switching characteristics are used where speed is more important, optimizing overall system performance.
Data Source
AI summary
According to one embodiment, a semiconductor integrated circuit 1 includes a sample and hold circuit and a clock generation circuit. The sample and hold circuit has a device with a first withstand voltage and a device with a second withstand voltage that is higher than the first withstand voltage. The clock generation circuit generates a first clock signal to be supplied to the first withstand voltage device and generates a second clock signal to be supplied to the second withstand voltage device based on the first clock signal. The clock generation circuit has a delay adjustment circuit that performs adjustment to delay the second clock signal and bring a phase of the second clock signal close to a phase of the first clock signal in the generation of the second clock signal.