Mixed Voltage CMOS Latch-Up Immunity via Segmented N-Well
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Solution Overview
Problem
Integrated circuits, particularly mixed voltage CMOS technology, face challenges in latch-up immunity due to parasitic bipolar current gains and shunt resistance issues, exacerbated by scaling and substrate doping changes, leading to noise injection and failure in space and military applications.
Innovation Solution
The implementation of diffused N-Tub structures embedded in P-wafers with retrograde N-wells and LDMOS implants in low voltage CMOS transistors, which reduce parasitic bipolar gains and shunt resistance, enhancing latch-up robustness without affecting P+/N+ space, and the use of shallow trench isolation to improve latch-up immunity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If scaling of standard CMOS technology is performed to reduce p+/n+ spacing, then device integration density is improved, but latch-up robustness deteriorates
Solution Approach 1:
The patent segments the N-well structure into two distinct parts: a first N-well region formed at a first depth and a second N-well region formed at a second depth greater than the first depth. This segmentation allows each well region to serve specific functions in suppressing parasitic bipolar transistors while maintaining close p+/n+ spacing for high integration density. The deep N-well acts as a guard ring to collect minority carriers and prevent latch-up, while the shallow N-well maintains device performance.
Solution Approach 2:
The patent introduces a vertical depth dimension to solve the lateral spacing problem. By forming N-well regions at different depths (first depth and second depth), the patent creates a three-dimensional well structure that provides latch-up immunity without increasing lateral spacing between p+ and n+ regions. The deep N-well extends vertically to intercept and neutralize minority carriers that would otherwise trigger latch-up in scaled devices.
2Object-affected harmful factors
If transition from p+ substrates to low doped p-substrates is performed, then noise performance is improved, but latch-up robustness deteriorates
Solution Approach 1:
The patent segments the substrate structure into multiple doped regions: low doped p-substrate for noise performance, deep N-well regions for latch-up suppression, and selectively doped regions. This segmentation allows the bulk substrate to maintain low doping for optimal noise performance while localized deep N-well regions provide the necessary doping concentration to suppress parasitic bipolar transistors and prevent latch-up.
Solution Approach 2:
The patent applies local quality by creating deep N-well regions with specific doping concentrations at particular locations within the low doped p-substrate. The doping concentration and depth of N-well regions are optimized locally to provide latch-up immunity only where parasitic bipolar transistors are most likely to form, while the rest of the substrate maintains low doping for superior noise performance in sensitive circuit regions.
3Length of moving object
If vertical scaling of wells is performed, then device miniaturization is improved, but lateral parasitic bipolar current gains increase
Solution Approach 1:
The patent addresses the issue by transitioning from purely lateral well structures to vertical well structures. The deep N-well regions extend significantly in the vertical dimension (depth) while maintaining compact lateral dimensions. This vertical scaling approach reduces the lateral base width of parasitic bipolar transistors by using the vertical depth to intercept carriers, thereby reducing lateral parasitic bipolar current gains while maintaining miniaturized device footprints.
Solution Approach 2:
The patent segments the well structure into shallow and deep components, where the deep N-well regions specifically target the suppression of parasitic bipolar transistors. The deep wells are positioned and dimensioned to intercept minority carriers before they can traverse the lateral base region, effectively breaking the regenerative feedback loop without requiring reduced lateral device dimensions.
4Ease of manufacture
If scaling of shallow trench isolation is performed to reduce aspect ratio, then manufacturing is simplified, but vulnerability to latch-up increases
Solution Approach 1:
The patent segments the isolation and well structures into coordinated components. The shallow trench isolation is maintained with simplified geometry for ease of manufacture, while deep N-well regions are formed that extend beneath the isolation structures. This segmentation allows the isolation to remain simple and manufacturable while the deep wells provide the necessary latch-up immunity that would otherwise require complex isolation geometries.
Solution Approach 2:
The deep N-well regions act as an intermediary structure that compensates for the reduced latch-up protection from simplified shallow trench isolation. By positioning deep wells at strategic locations where parasitic bipolar transistors may form, the patent provides an additional layer of protection that mediates between the simplified isolation structure and the requirement for latch-up immunity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively reduces latch-up occurrences by lowering parasitic bipolar current gains and shunt resistance, thereby improving the robustness of low voltage CMOS technology and enhancing its immunity to noise and voltage pulses, critical for space and military applications.
Implementation Method 1
a first dopant type structure embedded in a diffused deep well structure formed of a same dopant type of the first dopant type structure. The diffused deep well structure is associated with a non-isolated CMOS logic.
Implementation Method 2
diffused N-Tub structures embedded in P-wafers with retrograde N-wells
Implementation Method 3
the use of shallow trench isolation to improve latch-up immunity
Data Source
AI summary
Design structures, structures and methods of manufacturing structures for providing latch-up immunity for mixed voltage integrated circuits. The structure includes a diffused N-Tub structure embedded in a P-wafer and provided below a retrograde N-well to a non-isolated CMOS logic.