Mixed Voltage I/O ESD Device Using BJT and Resistor
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Solution Overview
Problem
Existing mixed-voltage tolerant input/output electrostatic discharge devices face issues with tunable ESD trigger voltages, low on-currents, and gate oxide breakdown, particularly in stacked n-channel field effect transistors (NFETs).
Innovation Solution
The solution involves replacing the top NFET in conventional stacked NFETs with a channel implanted resistor, utilizing a bipolar junction transistor (BJT) and a resistive element, which allows for higher on-current and tunable trigger voltage, and includes a silicide-blocking mask to prevent gate oxide breakdown.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If stacked NFETs are used for mixed-voltage applications, then device area is reduced, but on-current becomes too low
Solution Approach 1:
The invention divides the stacked NFET structure into separate active areas. Instead of implementing both NFETs in a single active area with minimum gate spacing, the patent uses separate active areas for each NFET, allowing each transistor to be optimized independently for current handling while maintaining compact overall layout.
Solution Approach 2:
The patent applies different design optimizations to different parts of the circuit. The first NFET is optimized for ESD protection with specific dimensional ratios, while the second NFET is optimized for driver functionality. This local optimization allows each component to perform its specific function effectively without compromising overall performance.
2Reliability
If stacked NFETs are used for mixed-voltage applications, then ESD protection is provided, but trigger voltage is not tunable
Solution Approach 1:
The patent enables trigger voltage tuning by modifying physical parameters of the NFET structure, specifically the width-to-length ratios of the transistors and the doping concentrations in the channel regions. By changing these parameters, the trigger voltage can be adjusted to match different ESD protection requirements while maintaining reliable ESD protection functionality.
3Ease of operation
If stacked NFETs are used for mixed-voltage applications, then driver functionality is achieved, but gate oxide breakdown occurs
Solution Approach 1:
The patent implements protective measures before gate oxide breakdown can occur by designing the NFET structure with adequate gate oxide thickness, optimized channel doping to reduce electric field concentration, and proper layout spacing. These preventive design choices cushion against the high electric fields that would otherwise cause gate oxide breakdown during ESD events or high-voltage operation.
Data Source
AI summary
An input/output (I/O) mixed-voltage drive circuit and electrostatic discharge protection device for coupling to an I/O pad. The device includes an NFET device having a gate, a drain, a source and body, the gate adapted for coupling to a pre-drive circuit, the source and the body being coupled to one another and to ground. The device also includes a bipolar junction transistor having a collector, an emitter and a base, the emitter being coupled to the drain of the NFET and the collector being coupled to the I/O pad.