Mixed-Voltage I/O Buffer With Gate Tracking for Leakage Control
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Solution Overview
Problem
Conventional mixed-voltage I/O buffers suffer from gate-oxide overstress, hot-carrier degradation, and unpredictable leakage currents when handling high voltage levels, leading to reliability issues in semiconductor devices.
Innovation Solution
The proposed mixed-voltage I/O buffer incorporates an output stage circuit with stacked pull-up P-type and pull-down N-type transistors, a dynamic gate bias generator, a gate-tracking circuit, and a floating N-well circuit to manage voltage levels and prevent leakage currents, along with an input buffer circuit that includes voltage level limiting and calibration mechanisms to handle varying input signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional mixed-voltage I/O buffer with one PMOS and one NMOS transistor is used, then the device structure is simple, but the device suffers from gate-oxide overstress, hot-carrier degradation and unpredictable leakage currents when handling high voltage levels
Solution Approach 1:
The output stage circuit is divided into multiple stacked transistors (first PMOS, second PMOS, first NMOS, second NMOS) instead of using a single PMOS and NMOS pair. This segmentation distributes the voltage stress across multiple devices, preventing gate-oxide overstress and hot-carrier degradation in any single transistor while maintaining overall circuit functionality.
Solution Approach 2:
A gate-tracking circuit is introduced as an intermediary component that dynamically adjusts the gate voltage of the first PMOS transistor based on the I/O pad voltage. This intermediary control mechanism prevents leakage currents and ensures proper transistor operation across different voltage levels without requiring a complete redesign of the basic buffer structure.
2Adaptability or versatility
If the output stage circuit uses high voltage levels (e.g. 5V) for signal transmission, then the signal transmission capability is improved, but the output stage circuit suffers from gate-oxide overstress and hot-carrier degradation
Solution Approach 1:
The gate-tracking circuit dynamically adjusts the gate voltage of the first PMOS transistor in real-time based on the I/O pad voltage level. This dynamic adaptation allows the circuit to handle various voltage levels (including high 5V signals) while automatically preventing gate-oxide overstress by ensuring the voltage differential across any single transistor remains within safe operating limits.
Solution Approach 2:
The circuit changes the operating parameters (gate voltages) of the transistors dynamically based on the input voltage level. By adjusting gate voltages rather than changing the physical transistor structure, the circuit achieves adaptability to different voltage levels while maintaining transistor reliability through controlled electric field conditions.
3Reliability
If stacked pull-up P-type transistors and stacked pull-down N-type transistors are used, then leakage current is prevented, but the device complexity increases
Solution Approach 1:
The single PMOS and NMOS transistors are segmented into stacked pairs (first PMOS with second PMOS, first NMOS with second NMOS). This segmentation creates multiple series connections that naturally suppress leakage currents by ensuring that all transistors in the stack must be simultaneously conductive, which is unlikely during normal operation. The segmentation approach addresses the leakage problem while keeping each individual transistor simple.
Data Source
AI summary
A mixed-voltage input/output (I/O) buffer includes an output buffer circuit. The output buffer circuit includes an output stage circuit, a gate-tracking circuit and a floating N-well circuit. The output stage circuit includes stacked pull-up P-type transistors and stacked pull-down N-type transistors, in which a first P-type transistor of the stacked pull-up P-type transistors and a first N-type transistor of the stacked pull-down N-type transistors are coupled to an I/O pad. The gate-tracking circuit controls gate voltage of the first P-type transistor in accordance with a voltage of the I/O pad to prevent leakage current. The floating N-well circuit provides N-well voltages for an N-well of the first P-type transistor and an N-well of a second P-type transistor, controlling gate voltage of the first P-type transistor, of the gate-tracking circuit to prevent leakage current.