Mixed-Voltage Semiconductor Layout for Leakage and Breakdown Control
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Solution Overview
Problem
Current semiconductor devices face challenges in integrating high-voltage, medium-voltage, and low-voltage transistors due to issues such as current leakage and breakdown voltage control, particularly as device scaling decreases.
Innovation Solution
A method for fabricating semiconductor devices that includes defining high-voltage, medium-voltage, and low-voltage regions on a substrate, forming transistors with specific gate dielectric layers and fin-shaped structures, and using a combination of etching, ion implantation, and epitaxial growth processes to create doped regions and gate electrodes, ensuring controlled threshold voltages and reduced leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If high-voltage devices and FinFET devices are integrated on the same chip, then device functionality and power efficiency are improved, but current leakage and breakdown voltage control become problematic
Solution Approach 1:
The chip is divided into distinct high-voltage regions and low-voltage regions with separate transistor structures. High-voltage transistors use planar structures with thicker gate dielectrics, while low-voltage transistors use FinFET structures with thinner gate dielectrics. This segmentation allows each region to be optimized for its specific voltage requirements without interference, solving the current leakage problem while maintaining integrated functionality.
Solution Approach 2:
Different transistor structures are implemented in different regions of the chip according to local requirements. The high-voltage regions employ planar transistors with adjusted doping profiles and thicker gate oxide, while low-voltage regions use FinFET structures. This local optimization enables breakdown voltage control in high-voltage areas and low leakage performance in low-voltage areas simultaneously.
2Productivity
If device scaling is reduced to increase integration density, then more devices can be integrated on a single chip, but breakdown voltage control and current leakage become more difficult
Solution Approach 1:
The invention segments the transistor population into high-voltage and low-voltage categories with structurally distinct implementations. This allows high integration density through compact FinFET structures in low-voltage regions while maintaining adequate breakdown voltage through planar structures in high-voltage regions, even as overall device dimensions are scaled down.
3Reliability
If planar MOS transistors are used for high-voltage operation, then breakdown voltage is achieved, but area occupancy increases and integration density decreases
Solution Approach 1:
The invention segregates high-voltage planar transistors and low-voltage FinFET transistors into separate regions. This allows the high-voltage planar transistors to occupy only the necessary area for high-voltage operation while FinFET structures handle the low-voltage functions more densely, optimizing the overall area utilization for mixed-voltage integration.
4Area of stationary object
If FinFET structures are used for low-voltage operation, then area efficiency and current drive are improved, but integration with high-voltage devices becomes challenging
Solution Approach 1:
The invention divides the device into separate high-voltage and low-voltage regions with clearly defined boundaries and isolation structures. This segmentation simplifies the integration process by allowing independent optimization of each region's transistor structures while maintaining compatibility through shared substrate and isolation architectures.
Solution Approach 2:
The invention implements local quality by tailoring transistor structures to specific voltage requirements in different regions. Low-voltage regions use FinFET structures for maximum area efficiency and current drive, while high-voltage regions use planar structures for adequate breakdown voltage, with each region independently optimized for its local performance requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the performance of semiconductor devices by improving current handling and breakdown voltage control, reducing leakage, and allowing for more effective integration of different voltage transistors on a single chip.
Implementation Method 1
forming a first gate dielectric layer on the first base
Implementation Method 2
using a combination of etching, ion implantation, and epitaxial growth processes to create doped regions
Implementation Method 3
using a combination of etching, ion implantation, and epitaxial growth processes to create doped regions
Data Source
AI summary
A semiconductor device includes a substrate having a high-voltage (HV) region, a medium-voltage (MV) region, and a low-voltage (LV) region, a HV device on the HV region, and a LV device on the LV region. Preferably, the HV device includes a first base on the substrate, a first gate dielectric layer on the first base, and a first gate electrode on the first gate dielectric layer. The LV device includes a fin-shaped structure on the substrate and a second gate electrode on the fin-shaped structure, in which a top surface of the first gate dielectric layer is lower than a top surface of the fin-shaped structure.