Mixed-Width Memory Repacking in Programmable Logic Devices
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Solution Overview
Problem
Programmable logic devices (PLDs) face challenges in implementing mixed-width mode memory components efficiently, as dedicated circuitry and logic are required, leading to increased size and complexity, especially in low-power, small-footprint devices, and under-utilization of embedded memory blocks when trying to implement mixed-width mode without dedicated resources.
Innovation Solution
The technique involves organizing fixed-mode embedded memory blocks in a cascaded manner and performing a memory repacking process to reduce or eliminate under-utilization, by reassigned and remapping control and data signals to share data across fewer memory blocks, allowing mixed-mode memory access without native support for mixed-mode access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If dedicated circuitry and logic are incorporated to support mixed-width mode memory access, then mixed-mode memory functionality is achieved, but the size and complexity of the PLD increases
Solution Approach 1:
The embedded memory blocks are designed to perform multiple functions - they can operate in fixed-mode for standard memory operations and be reconfigured through the repacking process to support mixed-width mode operations. The same physical memory blocks serve universal purposes, eliminating the need for dedicated mixed-mode circuitry.
Solution Approach 2:
The patent changes the operational parameters of the memory blocks through the repacking process. By reassigned and remapping control and data signals, the memory blocks transition from fixed-mode operation to mixed-width mode operation, achieving adaptability without adding physical circuitry.
2Adaptability or versatility
If multiple embedded memory blocks are organized into groupings to implement mixed-width mode without dedicated circuitry, then mixed-mode memory access is achieved, but the embedded memory blocks are under-utilized and valuable memory resources are wasted
Solution Approach 1:
The patent implements dynamic signal remapping where control and data signals are reassigned based on the specific memory access patterns required. This dynamic approach allows the same memory blocks to be fully utilized for mixed-width operations without waste, adapting the signal routing to match the operational requirements.
Solution Approach 2:
The patent introduces a new dimension of organization by implementing a repacking process that remaps signals across memory blocks in a cascaded manner. This dimensional reorganization of signal flow allows efficient utilization of memory resources for mixed-width mode without the under-utilization that occurs in traditional groupings.
3Adaptability or versatility
If fixed-mode embedded memory blocks are organized in a cascaded manner without repacking, then mixed-mode memory access is achieved, but significant under-utilization of memory blocks occurs
Solution Approach 1:
The patent performs preliminary repacking action during the design phase, where control and data signals are reassigned and remapped before the device is manufactured. This preliminary organization of signals ensures that when the device operates in mixed-width mode, the memory blocks are fully utilized without waste.
Solution Approach 2:
The patent creates a repacked version of the memory organization where signals are copied and remapped to different memory block configurations. This copying and remapping process allows the same physical memory blocks to be efficiently utilized for mixed-width operations, eliminating the under-utilization problem of direct cascaded organization.
Data Source
AI summary
Various techniques are provided to efficiently implement user designs in programmable logic devices (PLDs). In one example, a computer-implemented method includes receiving a design identifying operations to be performed by a PLD and synthesizing the design into a plurality of PLD components. The synthesizing includes detecting a mixed-mode memory operation in the design. The mixed-mode memory operation specifies memory access having different read and write data widths using a plurality of embedded memory blocks each having a fixed data width. The synthesizing further includes determining a reduced number of embedded memory blocks to implement the mixed-mode memory operation, and modifying the mixed-mode memory operation to remap the memory access to the reduced number of embedded memory blocks.