Mixed-Width TSV Layout for SoIC Power and Signal Stacking
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Solution Overview
Problem
Existing semiconductor packaging technologies face challenges in achieving high integration density and flexible design due to limitations in through substrate via (TSV) critical dimensions, which affect power and signal delivery, leading to high RC delay and IR drop issues in System-on-Integrated-Circuit (SoIC) stacking configurations.
Innovation Solution
Incorporating different TSV critical dimensions within a single solution for both power and signal delivery, allowing for multi-stacking beyond two-tier configurations, with larger TSVs for power and smaller TSVs for signal communication, thereby optimizing TSV area overhead and enabling high signal bandwidth and high-density integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If larger TSV critical dimensions are used, then power delivery capability is improved, but signal bandwidth and integration density deteriorate
Solution Approach 1:
The patent applies local quality by implementing different TSV critical dimensions in different regions of the substrate. First TSVs with larger critical dimensions are formed in a first region optimized for power delivery, while second TSVs with smaller critical dimensions are formed in a second region optimized for signal communication. This spatial differentiation of TSV dimensions allows each region to be optimized for its specific function, resolving the contradiction between power delivery capability and integration density.
2Productivity
If smaller TSV critical dimensions are used, then signal bandwidth and integration density are improved, but power delivery capability deteriorates
Solution Approach 1:
The patent implements local quality by creating region-specific TSV characteristics. In the first region, larger TSV critical dimensions provide low resistance paths for power delivery. In the second region, smaller TSV critical dimensions enable higher integration density and signal bandwidth. The substrate is thus divided into functional zones with optimized TSV dimensions for each zone's specific requirements.
3Ease of manufacture
If uniform TSV critical dimensions are used across the substrate, then manufacturing simplicity is maintained, but design flexibility and optimization for multiple functions deteriorate
Solution Approach 1:
The patent resolves this contradiction by implementing local quality through region-specific TSV dimensions. The manufacturing process is extended to include separate formation steps for first TSVs in a first region and second TSVs in a second region, allowing different critical dimensions. This approach sacrifices some manufacturing simplicity but gains significant design flexibility, enabling the substrate to simultaneously optimize for both power delivery and signal communication functions.
Data Source
AI summary
In an embodiment, a device may include a first structure comprising a first surface and a second surface opposite the first surface. The first structure may include a first substrate and a first through substrate via (TSV) exposed from the second surface of the first substrate. The first TSV may have a first width. The device may also include a second TSV exposed from the second surface of the first structure, where the second TSV has a second width smaller than the first width. The device may further include a guard ring surrounding each of the first and second TSVs. Additionally, the device may include a second structure bonded to the first surface of the first structure, where the first surface has first bond pads.