Double-Balanced Mixer Bias Circuit for Flicker Noise and IMD3
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Solution Overview
Problem
Double balanced mixers in communication circuits face challenges in reducing 3rd order harmonic (HD3) and inter modulation distortion (IMD3) while minimizing flicker noise, which affects signal quality and in-band emissions.
Innovation Solution
A transmitter system with a bias circuit that includes a programmable current source, a replica circuit, and a bias transistor to level shift the DC signal, maintaining a DC operating point that reduces the third order derivative of current (gm3) across temperature and process variations, and utilizing a common mode biasing scheme to eliminate differential flicker noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If bias circuits are added to reduce distortion and control operating points, then signal quality improves, but device complexity increases
Solution Approach 1:
The common mode bias generator serves multiple functions simultaneously: it sets the DC operating point for the transconductance stage, establishes the bias current level for distortion optimization, and provides the reference signal for the replica circuit. This multi-functionality reduces the need for separate circuits for each function.
Solution Approach 2:
The replica circuit automatically tracks and determines the optimal DC operating point of the transconductance stage through its inherent copying mechanism. The circuit self-adjusts to maintain the correct bias conditions without requiring external control or additional complexity, as the replica naturally mirrors the DC characteristics of the main circuit.
Data Source
AI summary
A transmitter that reduces 3rd order harmonic (HD3) and inter modulation distortion (IMD3) for a gm stage of a mixer while reducing flicker noise is disclosed. The transmitter may include a balanced mixer, a transconductance stage connected to the mixer, and a bias circuit. The bias circuit may include a programmable current source configured to provide a reference current. Further, the bias circuit may include a replica circuit configured to replicate a DC signal of the transconductance stage. The bias circuit may also include a bias transistor configured to level shift a bias signal obtained from a signal source based on the reference current and the DC signal of the transconductance stage as determined from the replica circuit.