Mixing-Mode DAC Duty-Cycle Feedback for Phase Mismatch Correction

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Solution Overview

Problem

Mixing-mode digital-to-analog converters (DACs) in wireless communication systems face issues with residual images and phase mismatches due to mismatches and timing errors, which previous techniques have not adequately addressed, even with duty-cycle correction attempts.

Innovation Solution

A closed-loop system incorporating a current comparison circuit and a duty cycle adjustment circuit is used to compare the currents output by the mixing-mode DAC and adjust the clock signal duty cycle, ensuring balanced current outputs and reducing phase mismatch.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If mixing-mode DAC is used for digital-to-analog conversion, then conversion efficiency is improved, but residual images and phase mismatches occur due to mismatches and timing errors

Engineering Contradiction:

Improveconversion efficiencyVSAvoidoutput accuracy

Core Design Contradiction:

ProductivityVSManufacturing precision

Solution Approach 1:

The patent implements a feedback mechanism where the output currents from the mixing-mode DAC are fed back to a duty cycle adjustment circuit. This circuit compares the actual output currents with the ideal balanced currents and adjusts the clock signal duty cycle accordingly to correct mismatches and eliminate residual images, thereby resolving the contradiction between conversion efficiency and output accuracy

Inventive Principle:

Principle #23Feedback

Solution Approach 2:

The patent dynamically changes the duty cycle parameter of the clock signal based on the detected current mismatches. By adjusting this critical parameter in real-time, the system optimizes the performance of the mixing-mode DAC to reduce phase mismatches and residual images while maintaining high conversion efficiency

Inventive Principle:

Principle #35Parameter changes

2Manufacturing precision

If duty cycle correction is applied to mixing-mode DAC, then phase mismatch is reduced, but residual images remain due to inadequate correction techniques

Engineering Contradiction:

Improvephase match accuracyVSAvoidresidual image elimination

Core Design Contradiction:

Manufacturing precisionVSReliability

Solution Approach 1:

The patent employs a continuous feedback loop where output currents are monitored and fed back to adjust the duty cycle. This closed-loop control ensures that both phase mismatches and residual images are addressed by continuously optimizing the clock signal duty cycle based on actual output conditions, providing more reliable correction than open-loop duty cycle techniques

Inventive Principle:

Principle #23Feedback

Solution Approach 2:

The duty cycle adjustment circuit automatically corrects its own control signal based on the detected output current mismatches. The system self-regulates the clock duty cycle without external intervention, dynamically eliminating residual images and phase mismatches through autonomous feedback control

Inventive Principle:

Principle #25Self-service

Data Source

PatentUS11184018B1Mismatch and timing correction technique for mixing-mode digital-to-analog converter (DAC)

Publication Date: 2021.11.23 QUALCOMM INC

AI summary

Certain aspects of the present disclosure generally relate to circuitry and techniques for digital-to-analog conversion. For example, certain aspects provide an apparatus for digital-to-analog conversion. The apparatus generally includes a mixing-mode digital-to-analog converter (DAC), a duty cycle adjustment circuit having an input coupled to an input clock node and having an output coupled to a clock input of the mixing-mode DAC, and a current comparison circuit having inputs coupled to outputs of the mixing-mode DAC and having an output coupled to a control input of the duty cycle adjustment circuit.