ML Anomaly Detection for SoC Protocol Bus Transactions
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Solution Overview
Problem
System-on-chip (SoC) development is a technically challenging and time-consuming process due to the difficulty in identifying anomalies during simulation and verification, particularly with millions of read and write transactions across various communication protocols, which can lead to errors in design verification.
Innovation Solution
An AI/ML-based anomaly detection system that classifies input signals from an SoC circuit using multi-layer perceptron neural networks to identify anomalies across different communication protocols, such as AXI4, PCIe, and USB, by separating read and write channel signals, normalizing data, and determining anomalies based on error thresholds, providing timely alerts and suggestions for corrections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If manual anomaly detection is used during SoC simulation and verification, then domain expertise can be applied to identify errors, but the process becomes time-consuming and tedious when dealing with millions of transactions across multiple protocols
Solution Approach 1:
The system enables self-service anomaly detection by training machine learning models to automatically identify anomalies in protocol bus transactions. The trained models process millions of transactions without requiring continuous human domain expertise intervention, thereby reducing development time while maintaining detection accuracy.
Solution Approach 2:
The system performs preliminary action by training machine learning models in advance on labeled transaction data before actual verification. This pre-training enables the system to rapidly detect anomalies during simulation without time-consuming manual analysis, resolving the contradiction between detection accuracy and development time.
2Reliability
If comprehensive verification of millions of transactions across multiple communication protocols is performed, then design errors can be detected, but the complexity of requiring domain expertise for each protocol increases
Solution Approach 1:
The system applies universality by creating a unified machine learning framework that handles multiple communication protocols (AXI4, PCIe, USB, etc.) through a single architecture. The model learns protocol-specific patterns during training and can universally detect anomalies across different protocols without requiring separate specialized systems for each protocol.
Solution Approach 2:
The system segments the verification task by training separate machine learning models for each communication protocol while using a unified anomaly detection framework. This segmentation allows the system to maintain high verification reliability for each protocol while managing complexity through modular, protocol-specific trained models.
3Measurement precision
If detailed analysis of each transaction is performed to ensure high anomaly detection accuracy, then design verification quality improves, but the processing time and computational resources increase
Solution Approach 1:
The system applies partial action by using machine learning models to focus detection efforts on transactions with higher anomaly probability. The trained models can identify suspicious patterns and prioritize detailed analysis of specific transactions rather than uniformly analyzing every transaction, thereby maintaining detection precision while improving verification throughput.
Data Source
AI summary
An anomaly detection system including: a primary processing device configured to receive one or more input signals from a simulated system on chip (SoC) circuit electrically coupled to the primary processing device and to classify the one or more input signals based on respective communication protocols of the one or more input signals; and a plurality of secondary processing devices communicatively coupled to the primary processing device, a secondary processing device from among the plurality of secondary processing devices being configured to receive signals from among the classified one or more input signals from the primary processing device, and to determine one or more anomalies in the received signals, the received signals having a communication protocol corresponding to the secondary processing device.


