ML ASIC Instruction-Rate Throttling for Overcurrent Control
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Solution Overview
Problem
The rapid evolution of machine learning applications necessitates short design and manufacturing cycles for ASICs, leading to potential overheating and damage due to power demands exceeding system capacity, resulting in shutdowns and loss of computation.
Innovation Solution
A system and method involving a voltage regulator that monitors current load, detects overcurrent conditions, and sends signals to an integrated circuit (IC) die to throttle processing rates using a throttling mask, synchronized with the IC's internal clock, to manage power usage and prevent overheating.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the ASIC operates at high power to meet evolving ML application demands, then computational productivity is improved, but the risk of overheating and damage increases
Solution Approach 1:
The system continuously monitors the actual power consumption of the ASIC and uses this feedback to dynamically adjust the instruction rate. The power management circuit receives power consumption information and modifies the throttling mask accordingly, creating a closed-loop control system that balances computational productivity with thermal safety.
Solution Approach 2:
The invention implements dynamic power management by allowing the ASIC's instruction rate to vary in real-time based on actual power consumption conditions. The throttling mask is continuously updated to reflect current operational state, enabling the system to adapt between high-performance mode and power-saving mode as needed.
2Reliability
If the power supply ceases power delivery when overcurrent threshold is exceeded, then system safety is improved, but computation continuity is lost
Solution Approach 1:
The invention introduces an intermediary throttling mechanism between the power supply and the ASIC. Instead of the power supply directly shutting down the ASIC when overcurrent occurs, the power management circuit acts as a mediator that throttles the instruction rate to prevent overcurrent conditions, thereby maintaining computation continuity while ensuring safety.
Solution Approach 2:
The system takes preliminary action by proactively throttling the instruction rate before overcurrent conditions can cause damage. The power management circuit monitors power consumption and adjusts the throttling mask in advance to prevent reaching dangerous current levels, avoiding the need for shutdowns.
3Strength
If the ASIC is shut down to prevent overheating, then hardware protection is improved, but computational availability decreases
Solution Approach 1:
The system dynamically adjusts the ASIC's operational state by modifying the instruction rate through throttling masks rather than complete shutdowns. This dynamic control allows the ASIC to operate at reduced capacity when approaching thermal limits, maintaining computational availability while providing hardware protection.
Solution Approach 2:
The invention changes the operational parameters of the ASIC by adjusting the instruction rate based on power consumption conditions. The power management circuit modifies the throttling mask to change the ASIC's processing speed, allowing continuous operation at varying performance levels rather than binary on/off states.
Data Source
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AI summary
A system contains a machine learning application specific integrated circuit (ASIC) and a power supply unit. The power supply unit and the ASIC are configured to be in data communication through dedicated pins on the ASIC and the power supply unit. The power supply unit detects a present power consumption of the ASIC. Upon determining that a threshold condition has been met, the power supply unit, responsive to the condition sends a digital signal to the ASIC. The ASIC contains a synchronizer which synchronizes the digital signal to be consistent with the ASICs internal clock frequency. A chip manager the synchronized signal and other signals to generate a throttling mask. The throttling mask is sent to a sequencer of the ASIC, which then limits the instruction flow into the processing units of the ASIC based on the mask. This in turn limits the power being consumed by the ASIC.