ML Buffer Tree Generation for Scalable Circuit Timing Design

The patent segments the circuit design problem into two distinct phases: (1) an initial phase using conventional net-level buffering techniques to achieve accurate timing results, and (2) a subsequent phase using machine learning models to rapidly generate buffer configurations that replicate the timing quality of the initial phase. This segmentation allows the computationally expensive accurate method to be applied only once, while the ML-based approach handles subsequent design iterations efficiently.

The patent performs preliminary action by training machine learning models in advance using data generated from conventional net-level buffering techniques. The trained models are then deployed to quickly predict buffer sizes and locations without requiring repeated execution of the computationally expensive dynamic programming algorithms, thus preserving timing precision while reducing computational time for actual circuit design tasks.

The patent segments the computational workload by separating the accurate but resource-intensive conventional buffering calculations from the rapid ML-based predictions. The conventional method is used only for training data generation and initial solutions, while the ML models handle the majority of buffer insertion tasks with minimal computational resources, thus maintaining timing precision while reducing overall computational resource consumption.

The patent creates simplified copies of the accurate buffer insertion behavior through machine learning models. These models are trained to replicate the timing optimization results of conventional net-level buffering but execute with fraction of the computational resources. The ML models serve as lightweight copies that preserve the essential timing optimization capabilities without the heavy computational overhead of the original conventional approach.

The patent segments the solution approach by using conventional net-level buffering only for generating training data and initial solutions on smaller or representative circuit portions. The machine learning models are then trained on this segmented data and applied to the entire large circuit, enabling the system to achieve accurate buffer placement on manageable subsets while scaling to handle much larger circuits that would be intractable with pure conventional methods.

The patent performs preliminary action by pre-training machine learning models on circuit data using conventional buffering techniques. This preliminary training phase captures the essential patterns and relationships for accurate buffer placement. Once trained, these models can be rapidly applied to large circuits without requiring the full computational overhead of conventional methods, thus improving scalability while preserving placement accuracy through the pre-learned knowledge.