Machine Learning Capacitance Extraction for Semiconductor Interconnects
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing methods for parasitic capacitance extraction in semiconductor technology face challenges with increasing complexity, including reduced modeling accuracy, increased calculation time, and pattern mismatch errors, especially with advanced structures and large chip scales.
Innovation Solution
An energy-efficient capacitance extraction method based on machine learning using a neural network model with a grid-based data representation and adaptive extraction window, combined with the XGBoost model, to efficiently extract self-capacitance and coupling capacitance in full-chip capacitance extraction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional pattern matching methods are used for capacitance extraction, then the extraction process is simple, but the accuracy decreases and errors accumulate due to pattern mismatch
Solution Approach 1:
The patent replaces the traditional mechanical pattern matching approach with a machine learning-based neural network system. The neural network learns complex patterns from training data and automatically identifies capacitance characteristics without requiring explicit pattern matching rules, thereby improving accuracy while managing complexity through automated learning processes.
Solution Approach 2:
The patent transforms the extraction problem by changing from discrete pattern matching to continuous parameter optimization. The neural network adjusts multiple parameters (weights, biases, activation functions) during training to minimize extraction errors, enabling high accuracy without relying on pre-defined patterns.
2Manufacturing precision
If advanced technology structures are modeled with higher accuracy, then the modeling precision improves, but the calculation time and complexity increase significantly
Solution Approach 1:
The patent performs preliminary action by pre-training the neural network on a comprehensive dataset of interconnection line structures before actual capacitance extraction. This offline training phase prepares the model to quickly and accurately extract capacitance values during production without requiring complex real-time calculations, thus reducing modeling time while maintaining high accuracy.
Solution Approach 2:
The patent creates a neural network model that copies and generalizes the complex physical relationships from training data. Instead of directly simulating complex electromagnetic fields during extraction, the pre-trained network replicates the learned patterns, enabling fast and accurate capacitance extraction without re-computing complex physics equations.
3Area of stationary object
If the chip scale increases, then the extraction coverage improves, but the workload and calculation resources required increase greatly
Solution Approach 1:
The patent replaces computationally intensive traditional extraction algorithms with a lightweight neural network inference system. Once trained, the neural network requires minimal computational resources to process each interconnection line, enabling energy-efficient capacitance extraction across large-scale chips without linearly increasing calculation energy consumption with chip size.
4Measurement precision
If traditional solvers are used to meet future chip design requirements, then the extraction accuracy can be maintained, but the energy consumption and calculation time increase
Solution Approach 1:
The patent creates a neural network that copies the accurate capacitance extraction capability from traditional solvers during the training phase. The network learns from high-accuracy reference solutions and replicates this accuracy during inference, achieving comparable precision to traditional solvers while consuming significantly less energy during actual extraction operations.
Data Source
AI summary
The present invention discloses an energy-efficient capacitance extraction method based on machine learning, and involves improving parameter extraction efficiency by using a machine learning model to extract parasitic capacitance; generally representing an interconnection line structure by grid-based data representation; reducing a workload of parameter extraction and enhancing the robustness of different semiconductor technologies with the idea of an adaptive extraction window; establishing a machine learning model of capacitance extraction for a two-dimensional interconnection line structure, and extracting grid parameters of a target interconnection line structure and inputting the grid parameters into the machine learning model, thereby obtaining parasitic capacitance parameters. Compared with an existing capacitance extraction technology, an capacitance extractor has achieved excellent performance in accuracy, speed and time and space consumption.