Chip Architecture Generation Using Machine Learning for Pareto Optimization
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Solution Overview
Problem
Integrated circuit design is challenging due to its complex nature and the large design space, with existing simulation tools unable to autonomously generate optimal chip architecture designs considering performance metrics and usage goals.
Innovation Solution
A trained machine learning model is used to determine selections of circuit building blocks and their arrangements on a chip, incorporating performance, power, and area constraints, employing techniques like unsupervised and supervised learning, and backpropagation to generate a chip architecture design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Extent of automation
If traditional simulation tools are used for chip design, then design flexibility is maintained, but the ability to autonomously generate optimal chip architecture designs is insufficient
Solution Approach 1:
The patent replaces traditional manual simulation-based design methods with a machine learning model that autonomously generates chip architectures. The ML model learns from training data containing chip architectures and their performance metrics, enabling automatic optimization without relying on conventional simulation tools, thereby resolving the contradiction between automation and complexity.
Solution Approach 2:
The patent transforms the design space into a learnable parameter space by training the ML model on chip architecture parameters and their corresponding performance metrics. The model learns optimal parameter configurations (power, latency, area) that satisfy design constraints, enabling autonomous generation of optimized architectures while managing design space complexity through learned patterns.
2Manufacturing precision
If the design space is extensively explored to find optimal architectures, then performance optimization is improved, but design time and computational resources increase
Solution Approach 1:
The patent performs preliminary action by training the ML model on a comprehensive dataset of chip architectures and their performance characteristics before actual design generation. This pre-learning phase captures optimal design patterns and relationships, enabling the model to quickly generate high-quality architectures during deployment without extensively exploring the design space each time, thus reducing design time while maintaining optimization quality.
Solution Approach 2:
The patent uses copying by training the ML model on existing chip architecture data and their performance metrics. The model learns to replicate and generalize optimal design patterns from the training data, enabling it to generate new architectures that inherit proven design principles without requiring exhaustive exploration of the entire design space, thereby achieving fast optimization.
3Productivity
If multiple performance metrics are optimized simultaneously, then overall chip performance is improved, but the complexity of balancing trade-offs increases
Solution Approach 1:
The patent applies universality by designing a single ML model that handles multiple performance metrics (power, latency, area) simultaneously. The model is trained to understand the relationships and trade-offs between these metrics, enabling it to generate architectures that optimize multiple objectives at once without requiring separate optimization processes for each metric, thus managing trade-off complexity while improving overall performance.
Solution Approach 2:
The patent uses feedback by training the ML model on performance metrics of generated architectures, allowing the model to learn from the outcomes and adjust its predictions. The model incorporates feedback about trade-offs between power, latency, and area from the training data, enabling it to automatically balance these competing objectives when generating new architectures, reducing the complexity of manual trade-off balancing.
Data Source
AI summary
Systems and methods for designing a chip configured to perform computing processes are provided. The described techniques include obtaining information associated with the chip and determining, using a trained machine learning model and the information associated with the chip, selections of one or more circuit building blocks to be included in the chip. The chip architecture may then be generated to be used in fabrication of the chip based on the selections of the one or more circuit building blocks.