Bit-Level Pruning of Technology-Mapped ML Circuits

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Solution Overview

Problem

Machine learning-related circuits, particularly those implemented with look-up tables (LUTs), are complex and costly due to over-provisioned components, making them inefficient to design and fabricate, especially when targeting hardware platforms with limited resources.

Innovation Solution

Bit-level pruning techniques are applied to technology-mapped circuits, replacing LUTs with constant logic states and optimizing the circuit design by removing or consolidating dependent LUTs, while evaluating the design's accuracy and metrics to minimize hardware components.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If machine learning circuits are implemented with trained models transformed into Boolean expressions using LUTs, then the circuit can perform machine learning functions, but the circuit becomes complex with many components and interconnections making it expensive to design and fabricate

Engineering Contradiction:
Improvemachine learning function implementationVSAvoidcircuit complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent extracts and removes redundant or less important components from the circuit. Specifically, it prunes LUTs and their interconnections that contribute minimally to the overall machine learning function, thereby reducing circuit complexity while preserving essential functionality. This is achieved through analysis of the trained model's weight magnitudes and their impact on output accuracy.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent applies different treatment to different parts of the circuit based on their importance. Instead of uniformly simplifying the entire circuit, it selectively prunes LUTs based on local criteria such as weight magnitude thresholds and their specific contribution to output accuracy. This allows critical regions to be preserved while non-critical regions are simplified or removed.

Inventive Principle:
Principle #3Local quality

2Measurement precision

If more LUTs and interconnections are used to implement the trained machine learning model, then the accuracy of the machine learning function is improved, but the cost of design and fabrication increases

Engineering Contradiction:
Improvemachine learning accuracyVSAvoiddesign and fabrication cost
Core Design Contradiction:
Measurement precisionVSEase of manufacture

Solution Approach 1:

The patent changes the parameter of LUT pruning by adjusting the weight magnitude threshold. By varying this threshold parameter, the system can control the degree of pruning and balance between accuracy and cost. Lower thresholds retain more LUTs for higher accuracy, while higher thresholds remove more LUTs to reduce cost, providing a tunable trade-off mechanism.

Inventive Principle:
Principle #35Parameter changes

3Device complexity

If LUTs are pruned at bit-level granularity to reduce circuit complexity, then the number of components is reduced, but it becomes challenging to maintain accuracy while achieving hardware savings

Engineering Contradiction:
Improvenumber of LUT componentsVSAvoidcircuit accuracy
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The patent employs feedback by evaluating the pruned circuit's accuracy using a validation dataset. After pruning LUTs based on weight magnitude thresholds, the system tests the pruned circuit against validation data and measures accuracy. This feedback loop allows iterative adjustment of pruning parameters to ensure that accuracy requirements are met while achieving maximum hardware reduction.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS20250111231A1Pruning of technology-mapped machine learning-related circuits at bit-level granularity
Publication Date: 2025.04.03 XILINX INC
  • US20250111231A1 patent drawing
  • US20250111231A1 patent drawing
  • US20250111231A1 patent drawing

AI summary

Embodiments herein describe pruning of technology-mapped machine learning-related circuits at bit-level granularity, including techniques to efficiently remove look-up tables (LUTs) of a technology-mapped netlist while maintaining a baseline accuracy of an underlying machine learning model. In an embodiment, a LUT output of a current circuit design is replaced with a constant value, and at least the LUT and LUTs within a maximum fanout-free cone (MFFC) are removed, to provide an optimized circuit design. The current circuit design or the optimized circuit design is selected as a solution based on corresponding training data-based accuracies and metrics (e.g., LUT utilization), and optimization criteria. If the optimized circuit design is rejected, inputs to the LUT may be evaluated for pruning. A set of solutions may be evaluated based on validation data-based accuracies and metrics of the corresponding circuit design. Solutions that do not meet a baseline accuracy may be discarded.