ML-Based Clustering for Clock Tree Synthesis

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Conventional clock tree synthesis techniques for integrated circuits are computationally expensive and time-consuming due to the need for multiple iterations of clustering to satisfy design rule constraints, especially when dealing with a large number of sinks.

Innovation Solution

A machine-learning model is trained to predict an initial number of clusters that satisfy design rule constraints, reducing the number of iterations required to achieve a valid clustering solution by using features such as driver location, sink sizes, and routing topology, and adjusting the number of clusters based on timing analysis results.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If conventional geometry-based or load-based clustering approaches are used with multiple iterations to satisfy design rule constraints, then clustering solution accuracy is improved, but computational time and resource consumption increase significantly

Engineering Contradiction:
Improveclustering solution accuracyVSAvoidcomputational time
Core Design Contradiction:
Manufacturing precisionVSLoss of time

Solution Approach 1:

The patent performs preliminary actions by estimating path delays and identifying clusters that violate design rule constraints before the main clustering optimization process. This preliminary analysis allows the subsequent clustering iterations to focus only on problematic clusters rather than re-evaluating all clusters, significantly reducing computational time while maintaining solution accuracy.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent segments the clustering problem by identifying and separating violator clusters from non-violator clusters. Instead of treating all clusters uniformly through multiple iterations, the method focuses computational resources only on clusters that violate design rule constraints, reducing the overall computational burden while achieving the same clustering solution accuracy.

Inventive Principle:
Principle #1Segmentation

2Reliability

If multiple iterations of reclustering are performed to satisfy design rule constraints, then design constraint satisfaction is improved, but computing resource utilization increases

Engineering Contradiction:
Improvedesign constraint satisfactionVSAvoidcomputing resource utilization
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent performs preliminary identification of violator clusters before the main clustering iterations. By pre-processing the data to identify which clusters violate design rule constraints, the subsequent iterations can focus computational resources only on these specific clusters, reducing overall computing resource utilization while ensuring design constraint satisfaction.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent extracts and isolates the violator clusters from the complete set of clusters. By separating the problematic clusters that need optimization from the already-satisfied clusters, the method reduces computing resource utilization by avoiding redundant evaluations of non-violator clusters across multiple iterations.

Inventive Principle:
Principle #2Taking out (Extraction)

3Manufacturing precision

If timing analysis is performed at each clustering iteration to evaluate clusters, then clustering quality is improved, but computational overhead increases

Engineering Contradiction:
Improveclustering qualityVSAvoidcomputational overhead
Core Design Contradiction:
Manufacturing precisionVSUse of energy by moving object

Solution Approach 1:

The patent performs preliminary estimation of path delays and identification of violator clusters before the main clustering iterations. This preliminary timing analysis allows subsequent iterations to focus only on clusters that may violate constraints, reducing computational overhead while maintaining clustering quality through targeted re-evaluation.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent segments the timing analysis workload by identifying and separating violator clusters from non-violator clusters. Instead of performing timing analysis on all clusters at each iteration, the method applies timing analysis only to violator clusters, reducing computational overhead while preserving clustering quality through focused evaluation.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS11645441B1Machine-learning based clustering for clock tree synthesis
Publication Date: 2023.05.09 CADENCE DESIGN SYST INC
  • US11645441B1 patent drawing
  • US11645441B1 patent drawing
  • US11645441B1 patent drawing

AI summary

Aspects of the present disclosure address systems and methods for performing a machine-learning based clustering of clock sinks during clock tree synthesis. An integrated circuit (IC) design comprising a clock net that includes a plurality of clock sinks is accessed. An initial number of clusters to generate from the set of clock sinks is determined using a machine-learning model. A first set of clusters is generated from the set of clocks sinks and includes the initial number of clusters. A timing analysis is performed to determine whether each cluster in the first set of clusters satisfies design rule constraints. The initial number of clusters is adjusted based on the timing analysis and a clustering solution is generated based on the adjusted number of clusters.