Decompression Accelerator for ML Model Inference Bottlenecks

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Solution Overview

Problem

Current decompression methods for machine learning model weights, typically performed in software, have limited throughput and become a bottleneck due to lower memory bandwidth and compute throughput, leading to modest performance in computing platforms during inference workloads.

Innovation Solution

A decompression accelerator is integrated with a processor core to offload weight de-sparsification and dequantization, enabling parallel decompression and matrix multiplication. The accelerator fetches compressed weights, decompresses them, and generates compatible weights for the processor core to process, improving throughput by controlling resource dimensioning for balanced memory and core bandwidth configurations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If software-based decompression is used, then device complexity is reduced, but productivity deteriorates due to limited throughput and memory bandwidth

Engineering Contradiction:
Improvedecompression throughputVSAvoidaccelerator structure
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The decompression function is extracted from the general-purpose processor and implemented as a dedicated accelerator unit. This separation allows the accelerator to be optimized specifically for decompression operations, achieving high throughput without requiring the full complexity of a general-purpose processor.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The accelerator serves as an intermediary component between memory and the processor. It receives compressed data from memory, performs decompression, and delivers decompressed data to the processor, thereby offloading the decompression burden from the processor and improving overall system productivity.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If decompression is performed by the processor core, then device complexity is minimized, but productivity deteriorates due to reduced compute throughput for inference workloads

Engineering Contradiction:
Improveinference workload performanceVSAvoidprocessor load
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The decompression workload is extracted from the processor core and assigned to a dedicated accelerator. This allows the processor core to focus entirely on inference computations, maximizing compute throughput while the accelerator handles decompression in parallel.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The system is segmented into two functional units: the processor core for inference workloads and the accelerator for decompression. This segmentation allows each component to be optimized for its specific function, improving overall system productivity.

Inventive Principle:
Principle #1Segmentation

3Productivity

If memory bandwidth is increased to improve decompression throughput, then productivity improves, but device complexity and cost increase

Engineering Contradiction:
Improvedecompression throughputVSAvoidmemory subsystem
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The accelerator acts as an intermediary that processes data locally before it needs to be transferred to the processor. By performing decompression closer to the data source, the accelerator reduces the amount of data that needs to be transferred over the memory bus, thereby reducing memory bandwidth requirements.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

Decompression is performed in advance before the data is needed by the processor. This preliminary action ensures that when the processor needs the decompressed data, it is already available, reducing wait time and improving throughput without requiring increased memory bandwidth.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS20250053454A1Methods and apparatus for a machine learning model decompression accelerator
Publication Date: 2025.02.13 INTEL CORP
  • US20250053454A1 patent drawing
  • US20250053454A1 patent drawing
  • US20250053454A1 patent drawing

AI summary

Systems, apparatus, articles of manufacture, and methods are disclosed for a machine learning model decompression accelerator. An example apparatus includes a processor core including at least one matrix multiplication engine, a memory storing a plurality of tiles of compressed data of a machine learning model to be processed by the at least one matrix multiplication engine; and a decompression accelerator including one or more control registers in communication with the processor core, a processing engine in communication with the memory and configured by the one or more control registers to decompress the plurality of tiles of the compressed data, and an output register to store decompressed data, wherein the processor core is to read the decompressed data from the output register and cause the at least one matrix multiplication engine to perform matrix multiplication with the decompressed data for execution of the machine learning model.