ML Defect Risk Modeling for Semiconductor Process Recipes
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Solution Overview
Problem
Semiconductor wafer processing faces challenges due to the complexity of optimizing multiple process steps and the limitations of in-line precision metrology, which often results in suboptimal process recipes and inefficient resource utilization.
Innovation Solution
The implementation of machine learning models trained on experimental data and expert knowledge to predict semiconductor device defects, allowing for the estimation of defect impact and optimization of process recipes, thereby reducing defect rates and improving manufacturing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If destructive metrology techniques like ICP-MS are used for precision measurement, then measurement precision is improved, but productivity deteriorates due to time consumption and inability to integrate into production line
Solution Approach 1:
The patent creates a virtual copy of the physical manufacturing process through a digital twin model. This digital model replicates the complex plasma etching process, allowing virtual experimentation and parameter optimization without consuming physical wafers or requiring destructive testing. The digital twin enables precise measurement and analysis of process parameters while maintaining full production throughput.
Solution Approach 2:
The patent replaces physical destructive measurement systems (ICP-MS) with computational modeling and simulation. Instead of using mass spectrometry to analyze physical samples, the system uses a digital twin to simulate and predict process outcomes, substituting mechanical/chemical analysis with computational analysis that provides the same precision without the drawbacks.
2Manufacturing precision
If design of experiment (DoE) is conducted with full wafers or portions for data collection, then manufacturing precision is improved, but loss of substance increases due to consumption of valuable wafers
Solution Approach 1:
The patent uses a digital twin to create virtual copies of wafers and process steps, enabling comprehensive DoE experimentation in the virtual domain. This allows extensive parameter variation and optimization studies without consuming any physical wafers, as all experiments are performed on digital replicas that can be reset and re-experimented indefinitely.
Solution Approach 2:
The patent performs all experimental design and parameter optimization in advance using the digital twin model before actual production begins. By completing the DoE virtually beforehand, the system identifies optimal parameters without needing to consume physical wafers during the experimentation phase, thereby eliminating wafer consumption associated with traditional DoE.
3Manufacturing precision
If the number of process steps is increased to handle shrinking device sizes, then manufacturing precision is improved, but device complexity increases making optimization difficult
Solution Approach 1:
The patent merges multiple discrete process steps and parameters into a unified digital twin model. Instead of managing and optimizing each individual process step separately, the digital twin integrates the entire multi-step plasma etching process into a single coherent simulation environment, allowing holistic optimization that accounts for interactions between steps while reducing the perceived complexity for engineers.
Solution Approach 2:
The digital twin model serves multiple functions simultaneously: it simulates process physics, predicts defect outcomes, optimizes parameters, and enables virtual experimentation. This multi-functional approach consolidates what would otherwise require multiple separate tools and processes, reducing overall system complexity while maintaining the capability to handle sophisticated multi-step processes.
Data Source
AI summary
A system includes a memory and a processing device, operatively coupled to the memory, to perform operations including receiving, as input to a trained machine learning model for identifying defect impact with respect to at least one type defect type, data associated with a process related to electronic device manufacturing. The data associated with the process comprises at least one of: an input set of recipe settings for processing a component, a set of desired characteristics to be achieved by processing the component, or a set of constraints specifying an allowable range for each setting of the set of recipe settings. The operations further include obtaining an output by applying the data associated with the process to the trained machine learning model. The output is representative of the defect impact with respect to the at least one defect type.