ML Delay Estimation for Emulation Timing Graph Routing

The patent segments the delay estimation process by dividing combinatorial paths into different categories based on their characteristics (e.g., path length, logic depth, routing complexity). Different delay estimation models are applied to different segments of paths, allowing accurate delay determination for each path type while avoiding the need for a completely new estimation system. This segmentation enables the system to achieve high measurement precision without overwhelming complexity.

The patent changes the parameters used in delay estimation by introducing multiple delay models that account for different path characteristics. Instead of using a single fixed estimation method, the system adjusts estimation parameters based on path type, logic depth, and routing complexity. This parameter adaptation allows accurate delay determination across diverse combinatorial paths while maintaining manageable process complexity through systematic parameter selection.

The patent applies preliminary action by performing delay estimation during the compilation process itself, rather than after. The system estimates delays for combinatorial paths as part of the compilation workflow, providing accurate timing information that guides placement and routing decisions. This preliminary delay determination enables faster emulation by avoiding iterative corrections and resource waste from incorrect delay calculations, while the estimation process is integrated into existing compilation steps to minimize additional time consumption.

The patent implements feedback mechanisms where delay estimation results are used to guide compilation decisions, and compilation results are fed back to refine delay estimates. The system uses initial delay estimates to perform placement and routing, then measures actual delays and uses this feedback to improve subsequent estimation accuracy. This feedback loop ensures that emulation runs at optimal speeds while minimizing time wasted on incorrect calculations by continuously refining delay determination based on actual performance data.

The patent applies local quality by tailoring delay estimation methods to specific path characteristics rather than applying a uniform detailed estimation to all paths. The system analyzes path properties such as length, logic depth, and routing complexity to determine the appropriate estimation level for each path. This localized approach ensures high measurement precision for critical paths while using minimal processing resources for less critical paths, optimizing the balance between accuracy and resource consumption.

The patent uses partial action by performing detailed delay estimation only for a subset of combinatorial paths that are most likely to be critical, rather than exhaustively analyzing all paths. The system identifies candidate critical paths based on heuristics and path characteristics, then applies detailed estimation only to these selected paths. This partial estimation approach achieves sufficient delay accuracy for optimization while significantly reducing processing resource consumption compared to complete path analysis.