ML Delay Estimation for IC Routing Accuracy
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Solution Overview
Problem
Current methods for estimating signal delays in circuit design, particularly for longer paths and those near device boundaries, are inaccurate, leading to difficulties in achieving timing closure and requiring excessive computational resources.
Innovation Solution
A machine learning model is trained using features of the integrated circuit's resistance-capacitance model to estimate delays between source and destination pins, reducing the need for extensive memory and computing resources while improving accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If more detailed modeling of more possible paths is used to improve delay estimation accuracy, then measurement precision improves, but device complexity and computing resources increase substantially
Solution Approach 1:
The patent segments the delay estimation problem by creating separate delay models for different path types (short paths, long paths, device boundary paths). Each segment uses appropriate modeling techniques, avoiding the need for a single complex model to handle all cases, thus improving accuracy without proportionally increasing overall complexity
Solution Approach 2:
The patent applies partial action by using simplified delay models for short paths where high accuracy is less critical, while applying more detailed modeling only to long paths and device boundary paths where accuracy is most needed. This selective approach improves overall delay estimation accuracy without requiring excessive computational resources for all paths
2Measurement precision
If more detailed modeling of more possible paths is used to improve delay estimation accuracy, then measurement precision improves, but memory and computing resources increase substantially
Solution Approach 1:
The patent divides the delay estimation task into segments based on path characteristics, allowing each segment to use optimized data structures and algorithms appropriate to its specific requirements. This reduces the memory and computing resources needed compared to a single comprehensive model that would need to handle all path types with equal detail
Solution Approach 2:
The patent applies local quality by using different levels of modeling detail in different regions of the design hierarchy. Device boundary paths and long paths receive detailed modeling attention, while short internal paths use simpler models, optimizing the balance between accuracy and resource consumption
3Device complexity
If current resistance-capacitance delay models are used, then device complexity remains low, but measurement precision deteriorates for longer paths and device boundary paths
Solution Approach 1:
The patent applies local quality by enhancing the delay model specifically for device boundary paths and long paths where the standard resistance-capacitance model fails. Instead of making the entire system complex, the patent adds targeted modeling capabilities only where needed, maintaining simplicity for short paths while improving accuracy for critical long paths
Solution Approach 2:
The patent changes the modeling parameters and approaches based on path characteristics. For device boundary paths, it introduces additional parameters and modeling techniques that account for boundary effects, while keeping the standard parameters for internal paths. This adaptive parameter approach improves accuracy without requiring a complete redesign of the modeling system
Data Source
AI summary
Training of a machine learning model used to infer estimated delays of circuit routes during placement and routing of a circuit design. Training can include selecting sample pairs of source pins and destination pins of an integrated circuit (IC) device, and determining respective delays of shortest paths that connect the source pins to the destination pins of the sample pairs based on a resistance-capacitance model of wires that form the shortest paths on the IC device. Respective sets of features are determined for the shortest paths, and the model is trained using the respective sets of features and the respective delays as labels. The machine learning model can be provided to an electronic design automation tool for estimating delays.