ML Delay Verification for IC Timing Closure
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Solution Overview
Problem
Current delay calculation algorithms in IC design face challenges with increasing complexity and accuracy requirements as technology advances to smaller process nodes, leading to difficulties in achieving timing closure and reliability, especially in modern SoC architectures and FPGA designs, where traditional methods like AWE show weaknesses in convergence and stability.
Innovation Solution
A method involving Machine Learning (ML) models for delay verification, including slew-rate, net-delay, and cell-delay models, which extract feature values from user designs to predict delays, iteratively refining the design to eliminate timing violations, utilizing ML inference cores and design flow tools for accurate and efficient delay calculation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional delay calculation algorithms (e.g., AWE) are used, then computational speed is maintained, but accuracy and reliability deteriorate due to convergence and stability weaknesses in modern SoC architectures
Solution Approach 1:
The patent replaces traditional mechanical/mathematical moment-matching algorithms (AWE, PRIMA, PVL) with a machine learning-based system. The ML model is trained offline using SPICE simulations to learn accurate delay characteristics, then performs fast inference during design iteration. This substitution achieves both high accuracy (comparable to SPICE) and reliability (deterministic ML inference) while maintaining computational speed.
2Measurement precision
If highly accurate electrical simulation (SPICE) is used, then measurement precision is improved, but computational time and complexity increase significantly
Solution Approach 1:
The patent performs the computationally intensive SPICE simulations in advance during an offline training phase to build the ML model. The trained model then captures the essential delay behavior, enabling fast online inference during design iteration. This preliminary action separates the heavy computational work from the iterative design process, achieving both accuracy and speed.
Solution Approach 2:
The patent creates a simplified copy of the complex SPICE simulation behavior through the ML model. Instead of running full SPICE simulations during iteration, the system uses the trained ML model that replicates SPICE's accuracy for delay prediction. This copying approach maintains measurement precision while dramatically reducing computational time.
3Adaptability or versatility
If traditional delay calculation methods are used, then ease of operation is maintained, but adaptability to new process nodes and architectures deteriorates
Solution Approach 1:
The patent adapts to new process nodes by changing the training data parameters rather than the algorithm structure. The ML model is retrained with SPICE simulations specific to the new process node characteristics (e.g., 7nm, 5nm). This parameter change approach allows the same ML framework to adapt to different technologies without increasing algorithmic complexity or requiring manual tuning.
Data Source
AI summary
A method for integrated circuit design with delay verification includes storing configuration files for a slew-rate Machine Learning (ML) model, a net-delay ML model and a cell-delay ML model. A user design is received, slew-rate feature values, net-delay feature values and cell-delay feature values are extracted from the user design, the configuration files are loaded to form inference cores, and operations of the slew-rate inference core are performed to calculate predicted slew-rate values that are sent to ML design tools. Operations of the net-delay inference core are performed to calculate predicted net-delay values that are sent to the ML design tools. Operations of the cell-delay inference core are performed to generate predicted cell-delay values that are sent to the ML design tools. The user design is iterated until a user design is obtained that is free of timing violations.