ML-Based DFT Recommendation for Scan Chain Optimization

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

The increasing complexity of integrated circuit (IC) designs and the limited number of automatic test equipment (ATE) ports lead to a dramatic increase in test application time (TAT) due to the need for long scan chains.

Innovation Solution

A machine-learning (ML)-based design-for-test (DFT) recommendation system is developed to optimize scan chain configuration by predicting the optimal test-case configurations for IC designs, considering features such as flip-flops, clock domains, faults, and test coverage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the number of scan chains is increased to cover more flip-flops, then test coverage is improved, but test application time increases dramatically

Engineering Contradiction:

Improvetest coverageVSAvoidtest application time

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent segments the scan chains into multiple groups and applies different compression techniques to different groups. Specifically, it divides scan chains into those that can be compressed and those that cannot, applying scan compression to the compressible groups while maintaining full scan for non-compressible groups, thereby reducing overall test application time while maintaining coverage

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent changes the parameter of scan chain configuration by identifying and applying compression to specific scan chains based on their compressibility characteristics. It modifies the test application process by compressing scan chains selectively rather than applying uniform full-scan or uniform compression across all chains

Inventive Principle:

Principle #35Parameter changes

2Loss of time

If scan compression is applied to reduce test application time, then test application time is reduced, but test coverage may be compromised

Engineering Contradiction:

Improvetest application timeVSAvoidtest coverage

Core Design Contradiction:

Loss of timeVSReliability

Solution Approach 1:

The patent segments scan chains into compressible and non-compressible groups, applying compression only to the former while maintaining full scan for the latter. This segmentation ensures that test coverage is not compromised because non-compressible chains retain their full testing capability

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent uses feedback from scan chain simulation and analysis to identify which scan chains are compressible and which are not. This feedback mechanism allows the system to make informed decisions about compression application, ensuring that compression is only applied where it will not harm test coverage

Inventive Principle:

Principle #23Feedback

3Reliability

If the number of ATE ports is increased to create more scan chains, then test coverage is improved, but device complexity and cost increase

Engineering Contradiction:

Improvetest coverageVSAvoidnumber of ATE ports

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent makes existing ATE ports multi-functional by using scan compression to allow a single port to handle multiple scan chains. The compression logic enables one ATE port to effectively test multiple scan chains sequentially, thereby reducing the total number of ports needed while maintaining the ability to test all flip-flops

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS12333227B1Machine-learning-based design-for-test (DFT) recommendation system for improving automatic test pattern generation (ATPG) quality of results (QoR)

Publication Date: 2025.06.17 SYNOPSYS INC

AI summary

A first set of features may be extracted from a first integrated circuit (IC) design. A trained machine learning (ML) model may predict a set of ranked test-case configurations for the first IC design based on the first set of features. A test-case configuration may correspond to a count of scan chain input and output ports and a scan chain length value.