Machine Learning EDA Platform for Chip Design Optimization

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Solution Overview

Problem

Conventional electronic design automation (EDA) tools require a time-consuming trial and error process for optimizing the placement and routing of standard library cells, leading to increased time to market and unnecessary duplication of design, simulation, and verification iterations.

Innovation Solution

The implementation of a machine learning-based electronic design automation platform that optimizes electronic architectural designs by adjusting geometric shapes, locations, and interconnections over multiple iterations to satisfy electronic design targets, reducing the need for manual adjustments and streamlining the design, simulation, and verification processes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of time

If conventional software tools are used for electronic device design, then design completeness is achieved, but time to market increases due to manual trial and error optimization

Engineering Contradiction:
Improvetime to marketVSAvoidmanual optimization process
Core Design Contradiction:
Loss of timeVSExtent of automation

Solution Approach 1:

The system performs self-service by automatically optimizing placement and routing of standard library cells through machine learning algorithms without requiring manual designer intervention. The EDA tool independently iterates through optimization cycles, adjusting cell positions and connections to meet design specifications, thereby eliminating the time-consuming manual trial-and-error process while maintaining design completeness.

Inventive Principle:
Principle #25Self-service

2Productivity

If manual trial and error optimization is performed, then design requirements are satisfied, but productivity decreases due to repetitive iterations

Engineering Contradiction:
Improvedesign iteration efficiencyVSAvoidplacement and routing optimization
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The patent replaces the mechanical manual trial-and-error process with an automated computational system using machine learning algorithms. The system substitutes human designer actions with algorithmic optimization that automatically adjusts placement and routing parameters, maintaining precision while dramatically improving productivity by eliminating repetitive manual iterations.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

3Loss of time

If conventional design tools complete placement and routing before optimization, then design structure is established, but time is wasted duplicating design, simulation, and verification across iterations

Engineering Contradiction:
Improveduplicate iteration timeVSAvoiddesign process complexity
Core Design Contradiction:
Loss of timeVSDevice complexity

Solution Approach 1:

The system performs preliminary action by establishing the complete design structure including placement and routing before initiating optimization iterations. This preliminary establishment allows subsequent optimization cycles to focus solely on improving existing structures rather than recreating them, thereby eliminating duplicate design, simulation, and verification work while managing process complexity through structured automation.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS11017149B2Machine-learning design enablement platform
Publication Date: 2021.05.25 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US11017149B2 patent drawing
  • US11017149B2 patent drawing
  • US11017149B2 patent drawing

AI summary

Electronic design automation (EDA) of the present disclosure, in various embodiments, optimizes designing, simulating, analyzing, and verifying of one or more electronic architectural designs for an electronic device. The EDA of the present disclosure identifies one or more electronic architectural features from the one or more electronic architectural designs. In some situations, the EDA of the present disclosure can manipulate one or more electronic architectural models over multiple iterations using a machine learning process until one or more electronic architectural models from among the one or more electronic architectural models satisfy one or more electronic design targets. The EDA of the present disclosure substitutes the one or more electronic architectural models that satisfy the one or more electronic design targets for the one or more electronic architectural features in the one or more electronic architectural designs to optimize the one or more electronic architectural designs. The EDA of the present disclosure can substitute the one or more electronic architectural models before, during, and/or after designing, simulating, analyzing, and/or verifying of the one or more electronic architectural designs to effectively decrease the time to market (TTM) for the electronic device.