ML-Guided Compiler Optimization for Register-Based Architectures

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Solution Overview

Problem

Current approaches to achieving peak performance for high performance computing (HPC) and machine learning (ML) applications on modern architectures are challenging due to the difficulty in predicting optimal compiler transformations, leading to suboptimal performance and lack of portability across hardware architectures and generations.

Innovation Solution

The use of machine learning-guided compiler optimizations that restrict the search space to register-based transformations, calculate accurate cost metrics, and identify optimal transformation sequences using Monte Carlo Tree Search algorithms, ensuring peak performance with minimal computational cost and scalability across multiple hardware architectures.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If traditional compiler optimizations are used, then application performance may be improved, but the complexity of predicting optimal transformations increases and portability across hardware architectures deteriorates

Engineering Contradiction:
Improveapplication performanceVSAvoidcomplexity of predicting optimal transformations
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent introduces an intermediary system consisting of a neural network model and Monte Carlo Tree Search algorithm that mediates between the source code and compiler transformations. This intermediary learns optimal transformation sequences from training data and applies them to new code, reducing the complexity of predicting optimal transformations while maintaining high application performance.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent performs preliminary action by training the neural network model on a large dataset of code examples and their optimal transformations before actual compilation. This pre-learning phase enables the system to quickly determine optimal transformations for new code without complex real-time analysis, improving both performance prediction accuracy and portability across different hardware architectures.

Inventive Principle:
Principle #10Preliminary action

2Productivity

If compiler transformations are applied to achieve peak performance, then computational cost increases, but without transformations performance remains suboptimal

Engineering Contradiction:
Improvepeak performanceVSAvoidcomputational cost
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

The patent applies partial action by selectively applying only the most beneficial compiler transformations identified by the neural network model, rather than exhaustively applying all possible transformations. The Monte Carlo Tree Search algorithm evaluates multiple transformation sequences and selects the optimal subset, achieving peak performance with reduced computational cost compared to exhaustive search methods.

Inventive Principle:
Principle #16Partial or excessive action

3Productivity

If compiler optimizations are designed for specific hardware architectures, then performance on those architectures improves, but scalability across multiple hardware architectures deteriorates

Engineering Contradiction:
Improveperformance on specific architectureVSAvoidscalability across hardware architectures
Core Design Contradiction:
ProductivityVSAdaptability or versatility

Solution Approach 1:

The patent implements universality by designing a hardware-agnostic neural network model that learns transformation patterns applicable across multiple hardware architectures. The model is trained on diverse code examples and can generalize to different target architectures, enabling the same compiler system to achieve peak performance on various hardware platforms without architecture-specific customization.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS11954466B2Methods and apparatus for machine learning-guided compiler optimizations for register-based hardware architectures
Publication Date: 2024.04.09 INTEL CORP
  • US11954466B2 patent drawing
  • US11954466B2 patent drawing
  • US11954466B2 patent drawing

AI summary

Methods, apparatus, systems, and articles of manufacture are disclosed that perform machine learning-guided compiler optimizations for register-based hardware architectures. Examples disclosed herein include a non-transitory computer readable medium comprising instructions that, when executed, cause a machine to at least select a register-based compiler transformation to apply to source code at a current position in a search tree, determine whether the search tree is in need of pruning based on an output of a query to a machine learning (ML) model, in response to determining the search tree is in need of pruning, prune the search tree at the current position, in response to applying the selected register-based compiler transformation to the source code, generate a code variant, calculate a score associated with the source code at the current position in the search tree, and update parameters of the machine learning (ML) model to include the calculated score.