ML-Assisted Hard Decision Decoding for NAND Flash Read Power

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Modern non-volatile memory systems, such as NAND flash memories, face significant power consumption challenges due to the high energy expenditure of error correction decoders, which is exacerbated by the need to correct bit errors in multi-level memory cells.

Innovation Solution

The implementation of a memory system that utilizes a machine learning algorithm, specifically a neural network, to generate reliability information for hard decision decoding, reducing the number of decoder iterations and thus lowering energy consumption by identifying reliable bits across adjacent pages.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If traditional error correction decoding is used on multi-level memory cells, then bit errors can be corrected, but power consumption increases significantly

Engineering Contradiction:
Improveerror correction capabilityVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent applies preliminary action by performing hard decision decoding on adjacent pages before the main decoding operation. This pre-processing step identifies and corrects obvious errors in neighboring pages, reducing the burden on the power-consuming iterative decoder for the current page. The decoder uses information from previously decoded adjacent pages to improve the efficiency of the current decoding operation.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent utilizes copying by leveraging the decoded data from adjacent pages as reference information for the current page decoding. The hard decision results from neighboring pages are copied and used to inform the decoding process of the target page, reducing the need for repeated iterative decoding operations and thereby lowering power consumption while maintaining error correction capability.

Inventive Principle:
Principle #26Copying

2Reliability

If iterative decoding is performed to correct errors in multi-level memory cells, then error correction efficiency improves, but the number of iterations increases power consumption

Engineering Contradiction:
Improveerror correction efficiencyVSAvoidenergy consumption per iteration
Core Design Contradiction:
ReliabilityVSLoss of energy

Solution Approach 1:

The patent applies partial action by performing hard decision decoding on only the adjacent pages rather than all pages, and using this partial information to assist the main decoding operation. This selective approach provides sufficient error correction capability while avoiding the excessive energy consumption that would result from processing all pages through the same intensive decoding process.

Inventive Principle:
Principle #16Partial or excessive action

3Productivity

If hard decision decoding is performed on all pages, then decoding speed increases, but error correction capability decreases

Engineering Contradiction:
Improvedecoding speedVSAvoiderror correction capability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent merges two different decoding approaches: hard decision decoding is applied to adjacent pages for speed, while the main page benefits from both hard decision results and soft information from the iterative decoder. This combination maintains high error correction capability for the critical data while achieving fast processing for adjacent pages, resolving the contradiction between speed and reliability.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS20230336188A1Hard decision decoding of non-volatile memory using machine learning
Publication Date: 2023.10.19 SAMSUNG ELECTRONICS CO LTD
  • US20230336188A1 patent drawing
  • US20230336188A1 patent drawing
  • US20230336188A1 patent drawing

AI summary

A memory system includes a plurality of memory cells each storing multiple bits and a memory controller having a processor. The memory controller is configured to read outputs from the memory cells in response to a read command from a host to generate first raw data of a first page and second raw data of a second page adjacent to the first page. The memory controller is further configured to perform a hard decision (HD) decoding on the first raw data to generate first decoded data. The processor is configured to apply the first decoded data and the second raw data as input features to a machine learning algorithm to generate reliability information. The memory controller is further configured to perform a HD decoding on the second raw data using the reliability information to generate second decoded data.