Machine Learning NoC Mapping for Scalable Interconnects

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Solution Overview

Problem

Traditional Network on Chip (NoC) architectures face challenges in optimizing performance and traffic customization due to scalability limitations, channel bandwidth constraints, and non-uniform traffic profiles, leading to sub-optimal power consumption and performance.

Innovation Solution

A method involving machine learning algorithms to determine and generate NoC mappings that meet specific cost functions, allowing for reconfiguration of NoC architectures to optimize performance across various traffic profiles by allocating routes, virtual channels, and layers, and supporting hardware reconfigurability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If traditional buses and crossbar based interconnects are used, then the design is simple, but scalability is limited

Engineering Contradiction:
Improveinterconnect design simplicityVSAvoidscalability
Core Design Contradiction:
Device complexityVSAdaptability or versatility

Solution Approach 1:

The interconnect is segmented into a network of routers and switches arranged in a topology (e.g., mesh, torus, 3D-torus) rather than a single monolithic bus. Each router operates independently and can be configured to handle different traffic patterns, enabling scalability while maintaining manageable complexity through modular design.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent transitions from 2D planar interconnects to 3D stacked architectures (e.g., 3D-torus, multi-layer mesh) by adding vertical interlayer routing. This dimensional expansion provides additional routing paths and increases bandwidth capacity without proportionally increasing planar area, thereby improving scalability.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Device complexity

If fixed NoC topology is used, then the hardware design is simple, but performance optimization for varying traffic profiles is poor

Engineering Contradiction:
Improvehardware design simplicityVSAvoidperformance optimization
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The NoC topology is made reconfigurable through hardware/software cooperation. Routers can dynamically adjust routing decisions based on current traffic conditions, and the topology can be reconfigured to adapt to different traffic profiles (e.g., computation-intensive vs. communication-intensive workloads) without requiring complete hardware redesign.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system changes operational parameters such as routing paths, virtual channel allocations, and switch configurations to optimize performance for specific traffic patterns. This allows the same physical hardware to achieve different performance characteristics by modifying software-controlled parameters rather than changing physical structure.

Inventive Principle:
Principle #35Parameter changes

3Reliability

If deterministic routing is used, then packet ordering is maintained and deadlocks are avoided, but load balancing across path diversities is not achieved

Engineering Contradiction:
Improvepacket ordering and deadlock freedomVSAvoidload balancing
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The routing function is segmented into multiple independent routing tables or policies that can be selectively applied. Different routing strategies (deterministic for reliability, adaptive for load balancing) can be applied to different traffic flows simultaneously, allowing the system to achieve both reliability for critical packets and load balancing for general traffic.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Instead of enforcing a single deterministic routing rule for all packets, the system inverts the approach by allowing flexible routing decisions and only applying determinism where necessary. This enables load balancing across multiple paths while maintaining packet ordering and deadlock freedom through selective application of routing policies.

Inventive Principle:
Principle #13The other way round (Inversion)

4Speed

If shortest path routing is used, then latency is minimized, but power consumption is not optimized for all traffic patterns

Engineering Contradiction:
Improvecommunication latencyVSAvoidpower consumption
Core Design Contradiction:
SpeedVSUse of energy by moving object

Solution Approach 1:

The routing strategy dynamically switches between shortest path and alternative paths based on real-time network conditions and traffic patterns. When the network is congested or power optimization is prioritized, the system can choose longer but less congested paths, thereby reducing overall power consumption while maintaining acceptable latency performance.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS10313269B2System and method for network on chip construction through machine learning
Publication Date: 2019.06.04 INTEL CORP
  • US10313269B2 patent drawing
  • US10313269B2 patent drawing
  • US10313269B2 patent drawing

AI summary

In example implementations, the specification is processed to determine the characteristics of the NoC to be generated, the characteristics of the flow (e.g. number of hops, bandwidth requirements, type of flow such as request/response, etc.), flow mapping decision strategy (e.g., limit on number of new virtual channels to be constructed, using of existing VCs, yx/xy mapping), and desired strategy to be used for how the flows are to be mapped to the network. In such processing, the machine learning algorithm can provide a determination as to if a flow is acceptable or not in view of the specification (e.g., via a Q score). In example implementations, the machine learning decisions can be applied on a flow by flow basis, and can involve supervised learning and unsupervised learning algorithms.