ML Hardware Overlay Mapping for Portable Acceleration
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Solution Overview
Problem
Conventional hardware acceleration of machine learning designs is inefficient, time-consuming, and not portable across different hardware accelerators due to manual customization and dependency on specific hardware, requiring reprocessing for each hardware generation.
Innovation Solution
An automated process translates machine learning primitives into an intermediate representation, subdivides them into functional compute blocks, and generates a synthesizable overlay for target hardware, leveraging adaptive hardware resources like GPUs and programmable logic to accelerate ML operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If manual analysis and customization is used for each ML operation, then hardware acceleration performance is improved, but design time and complexity increase significantly
Solution Approach 1:
The patent segments the ML design into standardized compute blocks that can be independently mapped to hardware accelerator resources. Each compute block represents a modular unit of computation that can be automatically instantiated and configured, eliminating the need for manual analysis of each operation while maintaining optimization capabilities.
Solution Approach 2:
The patent introduces an intermediate representation layer that sits between the high-level ML design and the hardware accelerator. This intermediate layer enables automatic translation and mapping of compute blocks to hardware resources, serving as a mediator that eliminates manual customization while preserving performance optimization.
2Power
If manual customization is performed for each hardware accelerator, then hardware-specific optimization is achieved, but portability across different hardware accelerators is lost
Solution Approach 1:
The patent creates a universal intermediate representation and standardized compute block framework that can be applied across different hardware accelerator types. The same intermediate representation can be mapped to various target hardware platforms, enabling portability while maintaining the ability to optimize for specific hardware characteristics through the mapping process.
3Manufacturing precision
If manual hardware adaptation is performed for each ML design, then custom optimization is achieved, but the process becomes cumbersome and difficult to maintain
Solution Approach 1:
The patent performs preliminary analysis and transformation of the ML design into an intermediate representation with standardized compute blocks before hardware mapping. This preliminary action captures optimization opportunities in a systematic way that can be automatically processed, reducing the complexity of the overall adaptation process while maintaining custom optimization capabilities.
Data Source
AI summary
Hardware acceleration of machine learning (ML) designs includes translating an ML primitive into an intermediate representation. The intermediate representation is subdivided to specify a functional compute block. The functional compute block is sized according to a compute node primitive adapted for implementing the ML primitive on target hardware. An overlay is generated for the ML primitive, at least in part, by mapping the functional compute block to the compute node primitive. The overlay is synthesizable to implement the ML primitive on the target hardware. The overlay can be scheduled for operation within the target hardware as part of an ML design including the ML primitive.