Machine Learning Parasitic Estimation for IC Design
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Solution Overview
Problem
Current integrated circuit (IC) chip design processes face challenges in accurately estimating parasitic resistance and capacitance between layers due to difficulties in predicting resistance in pre-route designs, leading to timing miscorrelation between pre-route and post-route designs.
Innovation Solution
A machine learning-based method is employed to determine parasitic resistance and capacitance values by training a machine learning model using a training set of IC designs, generating a density map, and applying it to pre-route designs to infer layer usage and via information, thereby improving the accuracy of parasitic RC estimation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional RC estimation methods are used in pre-route designs, then the design process can proceed quickly, but the parasitic resistance and capacitance values are inaccurate leading to timing miscorrelation
Solution Approach 1:
The patent applies preliminary action by training the machine learning model in advance using a training set of routed designs. This pre-computation phase enables the model to quickly estimate parasitic RC values during the actual pre-route design phase, achieving both high accuracy and fast processing time.
Solution Approach 2:
The patent uses copying by creating a density map that replicates the routing density patterns from routed designs. This density map serves as a surrogate representation that captures essential parasitic information without requiring full routed design computation, enabling accurate RC estimation in pre-route phase.
2Measurement precision
If detailed routed design information is used to estimate parasitic values, then accuracy improves, but the complexity of the design process increases
Solution Approach 1:
The patent extracts only the essential parasitic information needed for RC estimation by generating a density map from routed designs. This extraction approach captures critical routing density patterns while discarding unnecessary detailed routing information, reducing design process complexity while maintaining estimation accuracy.
Solution Approach 2:
The patent introduces a machine learning model as an intermediary between the routed design and parasitic RC estimation. This intermediary processes the density map and translates it into accurate RC values, simplifying the overall design process while maintaining high estimation accuracy.
3Productivity
If pre-route design is used for timing analysis, then the design flow is efficient, but the resistance between layers is difficult to predict leading to timing miscorrelation
Solution Approach 1:
The patent replaces traditional mechanical/computational RC extraction methods with a machine learning-based system. This substitution enables accurate parasitic RC estimation directly from pre-route designs by learning patterns from routed designs, maintaining design flow efficiency while improving timing analysis reliability.
Data Source
AI summary
Certain aspects are directed to apparatus and techniques for estimating parasitic information associated with routing of a design using a pre-route version of the design. One example method generally includes determining one or more output features using a machine learning model based on a pre-route version of a design of an integrated circuit, where the one or more output features include a density map providing an estimate of a density of elements associated with a routed version of the design. The method also includes estimating parasitic information associated with the design based on the one or more output features, and outputting the parasitic information.