ML Post-Route Path Delay Estimator from Synthesis Netlist
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Solution Overview
Problem
Current VLSI design processes face challenges in accurately predicting post-route quality of result (QoR) during the synthesis stage due to changes in combinational paths and routing parasitics, leading to inefficiencies in design space exploration and timing optimization.
Innovation Solution
A machine learning-based method using convolutional neural networks to predict post-route path delay from synthesis stage netlists, leveraging features like gate function, logic effort, and routing congestion, without requiring knowledge of backend algorithms, thus enabling faster and more accurate path delay estimation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional timing analysis at synthesis stage is used to predict post route QoR, then the prediction process is simple and fast, but the accuracy of path delay estimation deteriorates due to path changes and routing parasitics
Solution Approach 1:
The patent introduces a machine learning model as an intermediary between synthesis stage netlist and post route QoR prediction. The ML model learns the complex mapping from training data pairs (synthesis netlist features, actual post route delays) and serves as a mediator that translates synthesis stage information into accurate post route predictions without requiring direct complex physical analysis
Solution Approach 2:
The patent creates a virtual copy of the backend flow by training the ML model on actual backend flow outputs. The model learns to replicate the behavior of the complete backend flow (placement, routing, timing analysis) by copying patterns from training data, enabling fast predictions that mimic expensive sequential simulations
2Measurement precision
If backend flow is executed to obtain accurate post route QoR, then the prediction accuracy is high, but the time consumption increases significantly
Solution Approach 1:
The patent performs preliminary action by training the machine learning model in advance using training data generated from actual backend flow executions. Once trained, the model can rapidly predict post route QoR without executing the full backend flow again, enabling fast design space exploration while maintaining accuracy
Solution Approach 2:
The ML model creates a simplified copy of the expensive backend flow process. Instead of repeatedly executing the full backend flow for each design variant, the pre-trained model provides a fast approximation that captures the essential behavior, dramatically reducing time consumption while preserving prediction accuracy
3Productivity
If synthesis optimization is performed based on synthesis stage timing analysis, then the optimization process is fast, but the results deteriorate due to working on wrong critical paths
Solution Approach 1:
The patent introduces feedback by using the ML model to predict actual post route delays and feed this information back to guide synthesis optimization. Instead of relying solely on synthesis stage timing analysis which may identify wrong critical paths, the system uses predicted post route feedback to reliably identify true critical paths and guide optimization efforts
Solution Approach 2:
The patent replaces the mechanical synthesis stage timing analysis system with a machine learning-based prediction system. The ML model substitutes the traditional timing analysis mechanism, providing more reliable critical path identification by learning from actual post route outcomes rather than relying on approximate synthesis stage analysis
Data Source
AI summary
A neural network including an embedding layer to receive a gate function vector and an embedding width and alter a shape of the gate function vector by the embedding width, a concatenator to receive a gate feature input vector and concatenate the gate feature input vector with the gate function vector altered by the embedding width, a convolution layer to receive a window size, stride, and output feature size and generate an output convolution vector with a shape based on a length of the gate function vector, the window size of the convolution layer, and the output feature size of the convolution layer, and a fully connected layer to reduce the gate output convolution vector to a final path delay output.