Machine Learning Process Proximity Correction for Semiconductor Layouts
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Solution Overview
Problem
As semiconductor devices become highly integrated and nano-scale manufacturing technologies are applied, the increasing number of patterns in semiconductor layouts leads to significant computation challenges in correcting process errors during the etching process, necessitating improved methods for layout generation and correction.
Innovation Solution
A method involving machine learning-based process proximity correction (PPC) and optical proximity correction (OPC) is employed, where a computing device receives a first layout, performs machine learning-based inference on pattern features to generate a second layout, and then applies OPC to generate a third layout, reducing computational complexity and improving accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional OPC is applied to correct process errors in highly integrated semiconductor layouts, then manufacturing precision is improved, but computational complexity and processing time increase significantly
Solution Approach 1:
The patent segments the semiconductor layout into multiple regions and processes each region separately using machine learning models. This divides the computationally intensive task of correcting all patterns into smaller, manageable sub-tasks, reducing overall computational complexity while maintaining manufacturing precision through localized corrections
Solution Approach 2:
The patent replaces traditional rule-based optical proximity correction (OPC) algorithms with machine learning-based predictive models. This substitution transitions from deterministic mechanical correction rules to data-driven intelligent prediction, significantly reducing computational burden while improving pattern shape accuracy in highly integrated layouts
2Adaptability or versatility
If the number of patterns in semiconductor layout is increased for high integration, then device functionality is improved, but the amount of computation for layout correction increases sharply
Solution Approach 1:
The patent performs preliminary classification of patterns into different categories based on their geometric characteristics and proximity relationships before applying correction algorithms. This pre-processing step organizes the large number of patterns into structured groups, enabling more efficient batch processing and reducing the time required for layout correction in highly integrated devices
Solution Approach 2:
The patent changes the approach from individual pattern correction to region-based correction by transforming layout parameters into grid representations. This parameter transformation allows multiple patterns to be corrected simultaneously through field-based machine learning models, dramatically reducing correction time while maintaining the ability to handle high device integration
Data Source
AI summary
Disclosed is a method for fabricating of a semiconductor device. The method includes receiving a first layout including patterns for the fabrication of the semiconductor device, performing machine learning-based process proximity correction (PPC) based on features of the patterns of the first layout to generate a second layout, and performing optical proximity correction (OPC) on the second layout to generate a third layout.