ML Process Proximity Correction for Wafer Region Process Margins
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Solution Overview
Problem
Existing semiconductor manufacturing processes face challenges in maximizing process margins due to variations in critical dimensions and edge placement errors, particularly in areas and vertical heights within a wafer, leading to issues like bridging, pinching, and not-opening of patterns.
Innovation Solution
A machine learning-based process proximity correction (ML-PPC) method that predicts and corrects pattern deformations during etching and photo processes, generating layouts with maximized process margins by considering specific conditions such as area and vertical height, followed by optical proximity correction to ensure accurate pattern transfer onto masks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional OPC is performed without considering process variations, then manufacturing complexity is reduced, but manufacturing precision deteriorates due to variations in critical dimensions and edge placement errors across different wafer areas and heights
Solution Approach 1:
The patent divides the wafer into multiple regions (e.g., center, middle, edge areas) and applies different correction parameters to each region. This segmentation allows the system to account for process variations across different wafer areas and heights, improving critical dimension consistency without requiring a completely complex global correction model
Solution Approach 2:
The patent implements local quality by applying region-specific correction parameters to different areas of the wafer. Each region receives customized proximity correction based on its specific process characteristics, ensuring high manufacturing precision locally while maintaining manageable overall system complexity
2Manufacturing precision
If process proximity correction is performed for all conditions, then manufacturing precision is improved, but processing time increases due to multiple corrections for different areas and vertical heights
Solution Approach 1:
The patent performs preliminary process proximity correction on the layout data before optical proximity correction. By addressing process variations in advance during the PPC stage, the system reduces the need for extensive iterative adjustments later, thereby improving pattern formation accuracy while controlling overall processing time
Solution Approach 2:
The patent implements a dynamic correction approach where the degree of PPC application can be adjusted based on process conditions, pattern types, and wafer regions. This allows the system to optimize the balance between correction thoroughness and processing time, applying more aggressive corrections only where necessary
3Manufacturing precision
If machine learning-based PPC is applied to maximize process margin, then manufacturing precision is improved, but device complexity increases due to the need for prediction models and feature extraction
Solution Approach 1:
The patent introduces a machine learning prediction model as an intermediary between the input layout and the correction process. This model extracts relevant features from the layout and predicts process outcomes, enabling data-driven optimization of process margins while keeping the overall system architecture modular and manageable
Solution Approach 2:
The patent utilizes parameter changes by training the machine learning model on process data to learn optimal correction parameters. The model dynamically adjusts correction magnitudes and directions based on extracted features, maximizing process margins through adaptive parameter optimization rather than fixed correction rules
Data Source
AI summary
A machine learning (ML)-based process proximity correction (PPC) method includes receiving a first layout of an after clean inspection (ACI) including patterns for manufacturing a semiconductor device, extracting features of a first pattern from the first layout, generating a prediction model through ML based on the features of the first pattern, generating an ACI target having a maximum process margin by comparing an upper limit value and a lower limit value of the ACI for at least one condition, generating a second layout of an after development inspection (ADI) by correcting the first layout to correspond to the ACI target, and predicting the ACI through the prediction model, based on the second layout of the ADI.