ML-Based Resource Estimation for IC Circuit Design
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Solution Overview
Problem
In Electronic Design Automation (EDA) tools, users lack early-stage information about the resource requirements of circuit designs for integrated circuits (ICs), leading to significant redesign efforts when the design is found too large for the target IC, often discovered late in the process.
Innovation Solution
The use of machine learning (ML) models specific to each Intellectual Property (IP) core to estimate resource usage by providing input on the target IC and parameterizations, allowing for early resource usage estimation during the design process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If detailed resource usage information is obtained through synthesis, placement, and routing operations, then measurement precision is improved, but the timing of information availability shifts to late stages of the design process
Solution Approach 1:
The patent applies preliminary action by performing resource usage estimation before the traditional synthesis, placement, and routing operations. Machine learning models are trained on historical design data to predict resource requirements in advance, allowing users to obtain accurate resource usage information at early design stages rather than waiting for late-stage operations to complete.
Solution Approach 2:
The patent replaces the traditional mechanical/electronic design verification process (synthesis, placement, routing) with a computational approach using machine learning models. These ML models process design parameters and IP core characteristics to estimate resource usage, substituting the time-consuming physical design verification with faster computational prediction.
2Manufacturing precision
If traditional design verification is performed late in the process, then manufacturing precision is improved, but productivity deteriorates due to significant redesign efforts
Solution Approach 1:
The patent enables preliminary verification of circuit design fit to target IC by using machine learning models to predict resource usage before final design completion. This allows users to identify potential sizing issues early and adjust their designs accordingly, preventing costly redesign efforts while maintaining manufacturing precision.
Solution Approach 2:
The patent implements feedback mechanisms by providing users with real-time resource usage estimates during the design process. The machine learning models analyze design parameters and IP core configurations to give immediate feedback on resource requirements, enabling users to adjust their designs to fit target IC constraints without waiting for late-stage verification.
3Productivity
If machine learning models are used for early estimation, then productivity is improved through early-stage resource usage knowledge, but device complexity increases due to model selection and training requirements
Solution Approach 1:
The patent uses copying by creating machine learning models that replicate the resource usage characteristics of IP cores based on their parameters and configurations. These models serve as virtual copies that can be rapidly instantiated and evaluated without requiring actual physical implementation or complex manual analysis, simplifying the verification process while maintaining accuracy.
Data Source
AI summary
Resource estimation for implementing circuit designs in an integrated circuit (IC) can include detecting, using computer hardware, a plurality of Intellectual Property (IP) cores within a circuit design, extracting, using the computer hardware and from the circuit design, parameterizations for the plurality of IP cores as used in the circuit design, and selecting, using the computer hardware, a machine learning (ML) model corresponding to each IP core, wherein each selected ML model is specific to the corresponding IP core. Each selected ML model can be provided input specifying a target IC for the circuit design and the parameterization for the corresponding IP core. An estimate of resource usage for the circuit design can be generated by executing the selected ML models. The resource usage specifies an amount of resources of the target IC needed to implement the circuit design in the target IC.


