ML Scan Chain Grouping for Area and Power Optimization
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Solution Overview
Problem
Conventional scan chain testing methods occupy a significant portion of the real estate area in electronic devices due to inefficient grouping and ordering of scan flip-flops, which affects power, performance, and area optimization in electronic circuitry.
Innovation Solution
An electronic design automation platform that uses machine learning for grouping and ordering scan flip-flops into scan chains based on shared characteristics, optimizing power, performance, and area by performing mathematical cluster and routing analyses, and filtering out outliers to minimize resource usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional scan chain testing methods are used with traditional grouping and ordering, then fault detection capability is maintained, but real estate area consumption increases significantly (occupying 10-40% of device area)
Solution Approach 1:
The patent applies parameter changes by using machine learning algorithms to optimize the grouping and ordering parameters of scan flip-flops. The system learns from design characteristics and adjusts grouping parameters to minimize area consumption while maintaining test effectiveness, reducing scan chain area from 10-40% to lower values.
Solution Approach 2:
The patent replaces traditional mechanical/manual scan chain design methods with an automated machine learning-based system. The ML platform automatically performs cluster analysis and routing optimization, substituting conventional trial-and-error or rule-based approaches with intelligent algorithms that optimize area utilization.
2Reliability
If more scan chains are placed in electronic devices to improve test coverage, then fault detection capability improves, but power consumption and area usage increase
Solution Approach 1:
The machine learning platform optimizes the number and configuration parameters of scan chains by analyzing design characteristics and test requirements. It determines the minimum necessary scan chains to achieve adequate test coverage while minimizing power consumption and area usage, avoiding over-provisioning of test resources.
Solution Approach 2:
The patent applies local quality by creating heterogeneous scan chains tailored to specific circuit regions and fault types. Different scan chains are optimized for different areas of the device, with grouping strategies adapted to local circuit characteristics, allowing efficient test coverage without uniformly increasing power consumption across the entire device.
3Ease of manufacture
If traditional scan chain grouping methods are used, then implementation simplicity is maintained, but resource optimization (power, performance, area) deteriorates
Solution Approach 1:
The machine learning platform performs self-service by automatically analyzing design inputs, performing cluster analysis, determining optimal grouping and ordering, and generating implementation-ready outputs without manual intervention. This automation maintains ease of manufacture while achieving superior power, performance, and area optimization compared to manual methods.
Solution Approach 2:
The patent replaces manual scan chain design processes with automated machine learning algorithms. The ML system substitutes traditional engineer-driven trial-and-error methods with intelligent automation that optimizes resource utilization while maintaining simple integration into the design flow through automated toolchains.
Data Source
AI summary
Electronic design automation (EDA) of the present disclosure, in various embodiments, optimizes designing, simulating, analyzing, and verifying of electronic circuitry for an electronic device. The electronic device includes scan flip-flops to autonomously test the electronic circuitry for various manufacturing faults. The EDA of the present disclosure statistically groups the scan flip-flops into scan chains in such a manner such that scan flip-flops within each scan chain share similar characteristics, parameters, or attributes. Thereafter, the EDA of the present disclosure intelligently arranges ordering for the scan flip-flops within each of the scan chains to optimize power, performance, and/or area of the electronic circuitry.