Machine Learning Voltage Drop Prediction for 3D Stacked Devices
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Solution Overview
Problem
Predicting voltage drops on a 3D power distribution network (PDN) is challenging due to increased logic density, non-uniform current loads, and misalignment of circuit elements, which can lead to functional failures and performance degradation in 3D stacked semiconductor devices.
Innovation Solution
A machine learning (ML) based method for predicting voltage drops on a 3D PDN involves receiving spatial power distribution and source node location maps, dividing them into overlapping windows, determining voltage drop maps for each window, and combining these maps to form a composite voltage drop map for the entire semiconductor die layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional methods are used to solve the system of linear equations for PDN analysis, then voltage at every node can be determined, but computational cost becomes excessively high due to millions of nodes
Solution Approach 1:
The patent divides the large-scale PDN into multiple smaller sub-networks or clusters of nodes. Instead of solving the complete system of linear equations for all millions of nodes simultaneously, the network is segmented into manageable portions that can be analyzed independently or with reduced computational coupling, significantly lowering the computational burden while maintaining voltage prediction accuracy.
Solution Approach 2:
The patent creates simplified representative models or copies of the PDN structure that capture the essential electrical characteristics without replicating every single node. These reduced-order models are used for rapid voltage drop analysis, providing accurate predictions without the computational expense of full-scale simulation.
2Productivity
If 3D stacked device topology is implemented to increase bandwidth, then connectivity among ICs improves, but voltage (IR) bottlenecks increase due to misalignment of circuit elements and connections
Solution Approach 1:
The patent applies local quality analysis by examining specific regions of the 3D PDN where misalignment occurs between circuit elements and vertical connections (TSVs, bumps). The method identifies local IR drop hotspots caused by misalignment and applies targeted correction or optimization to those specific areas, rather than treating the entire PDN uniformly, thereby maintaining voltage stability without sacrificing bandwidth.
Solution Approach 2:
The patent extends traditional 2D PDN analysis methods to three dimensions by incorporating the vertical dimension where TSVs and bumps connect different die layers. This 3D-aware analysis captures the complex current paths and IR drops that occur in the vertical direction due to misalignment, enabling accurate voltage prediction in stacked device topologies while preserving the high bandwidth benefits.
3Productivity
If circuit elements are densely packed in 3D PDN to increase logic density, then functionality improves, but current drawn per unit area increases leading to higher IR drops
Solution Approach 1:
The patent performs preliminary voltage drop analysis and identification of high-current-density regions during the design phase, before final fabrication. By detecting areas where dense packing causes excessive IR drops, the method enables early optimization of power distribution routing, insertion of additional power sources, or adjustment of cell placement to balance current distribution, thereby reducing power loss while maintaining high logic density.
Data Source
AI summary
A method for predicting voltage drop on a power delivery network of a 3D stacked device includes receiving a spatial power distribution map of a plurality of semiconductor dies of the 3D stacked device, receiving a spatial power source node location map for a plurality of power source nodes coupled to the 3D stacked device, dividing vertically the spatial power distribution map and the spatial power source node location map into overlapping windows, determining a voltage drop map in each of the windows based on the divided spatial power distribution map and the divided spatial power source node location map, and combining the voltage drop map in each of the windows to form a composite voltage drop map.