Semiconductor Layout Simulation Using ML Wafer Image Prediction
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Solution Overview
Problem
Existing optical proximity correction (OPC) and process proximity correction (PPC) methods for semiconductor integrated circuits are computationally intensive and rely on partial pattern information, leading to potential errors in the fabrication process.
Innovation Solution
A method using machine learning-based semiconductor layout simulation, employing a semiconductor layout simulation module that includes a wafer image generator, discriminator, and updater, to generate and validate wafer images based on multi-channel images, including layout, fabrication device, and density information, without distinguishing between OPC and PPC processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If CD-based or contour-based OPC and PPC methods are used, then manufacturing precision can be improved, but computational complexity and time increase significantly
Solution Approach 1:
The patent replaces traditional mechanical/computational OPC and PPC methods with a machine learning-based simulation module. The module uses trained neural networks to predict wafer images directly from layout images, substituting the complex iterative computational processes with a trained model that provides both high accuracy and reduced computational burden.
Solution Approach 2:
The system performs preliminary training of the machine learning model using extensive OPC and PPC data beforehand. Once trained, the model can quickly predict wafer images without requiring real-time complex computations. The pre-computed knowledge is stored in the model weights, enabling fast inference during actual layout simulation.
2Manufacturing precision
If CD-based or contour-based OPC and PPC methods are used, then manufacturing precision can be improved, but the process becomes slower and less efficient
Solution Approach 1:
The patent replaces traditional mechanical/computational OPC and PPC methods with a machine learning-based simulation module. The module uses trained neural networks to predict wafer images directly from layout images, substituting the complex iterative computational processes with a trained model that provides both high accuracy and reduced computational burden.
3Reliability
If traditional OPC and PPC methods are used, then partial pattern information can be processed, but measurement precision and reliability decrease
Solution Approach 1:
The machine learning simulation module is trained on diverse data including layout images, wafer images, and corresponding OPC/PPC results. This enables the single model to handle various pattern types and fabrication conditions universally, improving both reliability and measurement precision across different semiconductor manufacturing scenarios.
Data Source
AI summary
Disclosed is an operating method of an electronic device which includes a processor executing a semiconductor layout simulation module based on machine learning. The operating method includes receiving, at the semiconductor layout simulation module executed by the processor, a layout image, inferring a wafer image based on the layout image and a fabrication device information image of a semiconductor fabrication device fabricating a semiconductor integrated circuit based on a final layout image, adjusting the layout image when the wafer image is not acceptable, and confirming the layout image as the final layout image when the wafer image is acceptable.