MLA Current Surge Management via Dynamic Clock Adjustment
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Solution Overview
Problem
Machine learning networks implemented in edge devices face significant power consumption challenges due to concurrent execution of statically scheduled instructions, leading to current surges that stress power supplies and cause voltage fluctuations, potentially resulting in functional failures and long-term chip damage.
Innovation Solution
A machine learning accelerator (MLA) with digital power control manages current consumption by estimating execution demands and adjusting the clock frequency using monitor circuits, aggregator logic, and a clock controller to mitigate current surges, employing digital circuits for fast control loops and simplifying hardware design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If concurrently executed statically scheduled instructions are used to improve processing speed, then productivity is improved, but current consumption increases causing voltage fluctuations and reliability deterioration
Solution Approach 1:
The patent implements dynamic clock frequency adjustment based on real-time current consumption monitoring. The clock controller dynamically modifies the clock frequency signal according to activity metrics from monitor circuits, allowing the system to adapt between high-performance and low-power states, thus resolving the contradiction between processing speed and voltage stability
Solution Approach 2:
The patent employs a feedback mechanism where monitor circuits continuously measure current consumption activity metrics, which are then fed to the clock controller. This closed-loop feedback enables the system to automatically adjust clock frequency in response to actual power consumption conditions, preventing voltage fluctuations while maintaining optimal processing speed
2Productivity
If clock frequency is increased to improve processing speed, then productivity is improved, but power consumption increases causing harmful thermal and electrical effects
Solution Approach 1:
The patent implements periodic clock gating where the clock signal is selectively enabled or disabled based on whether compute elements are actively executing instructions. By using the clock signal periodically rather than continuously, and by gating the clock to compute elements only when needed, the system reduces average current consumption and eliminates harmful current surges while maintaining processing speed when computation is required
3Device complexity
If simplified on-chip compute elements are used to conserve resources, then device complexity is reduced, but measurement precision of power consumption control deteriorates
Solution Approach 1:
The patent introduces monitor circuits as intermediary components between the simplified compute elements and the clock controller. These monitor circuits precisely measure current consumption activity metrics without adding significant complexity to the compute elements themselves, enabling accurate power consumption control while maintaining hardware simplicity
Solution Approach 2:
The patent replaces complex hardware power management mechanisms with a software-controlled clock frequency adjustment system. The compiler generates code with explicit power management instructions, and the clock controller executes these software-based control commands, substituting mechanical/hardware complexity with software intelligence to achieve precise power consumption control
Data Source
AI summary
Current surge is managed by estimating the current demand based on the actual instructions being executed and then adjusting the clock for the static schedule. For statically scheduled instructions, the compute elements synchronously execute the instructions according to the static schedule. The synchronization is provided by a common clock that is used to clock the instruction execution by the compute elements. As instructions are being executed, their current consumption may be estimated based on the type of instruction. The current consumptions for the instructions executed by the compute elements may be aggregated, providing an estimate of the aggregate current demand. This can then be used to adjust the clock accordingly.