Multi-Level Cell 1S1R Memory Using Voltage Pulse Tuning
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Solution Overview
Problem
Conventional 3D cross-point memory arrays using transistor switches face scalability limitations due to the need for high programming current, which restricts density and increases costs, while one-selector-one-resistor (1S1R) structures offer high density but struggle with precise control of intermediate resistance states for multi-level cell (MLC) capabilities.
Innovation Solution
A multi-level cell (MLC) 1S1R structure is implemented using a stacked arrangement of a phase change memory (PCM) cell and a chalcogenide-based ovonic threshold switch (OTS) selector, allowing for voltage pulses to tune the PCM cell into fully set, fully reset, or intermediate states, enabling storage of additional data at intermediate voltage levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If transistor switches are used in 3D cross-point memory arrays, then control capability is improved, but device complexity and cost increase while scalability is limited due to high programming current requirements
Solution Approach 1:
The patent extracts the switching function from traditional transistor switches and implements it using a threshold switch element instead. This threshold switch is integrated into the cross-point memory array, allowing control capability to be maintained while reducing device complexity and eliminating the need for high programming currents that limited scalability in transistor-based systems
Solution Approach 2:
The patent uses a threshold switch element that replicates the switching functionality of transistors but with simplified structure. The threshold switch copies the essential control capability while removing the complex gate structure and high current requirements of traditional transistors, enabling scalable high-density memory arrays
2Productivity
If 1S1R structures are used to achieve high density, then scalability is improved, but manufacturing precision is worsened due to difficulty in controlling intermediate resistance states for MLC capabilities
Solution Approach 1:
The patent applies dynamic voltage pulsing schemes to control the phase change material's resistance states. By using sequences of voltage pulses with varying amplitudes and durations, the system can dynamically transition between different resistance states (fully set, fully reset, and intermediate states), enabling precise control of MLC data states while maintaining high scalability of the 1S1R structure
Solution Approach 2:
The patent changes the voltage parameters (amplitude, duration, sequence) applied to the phase change material to achieve different resistance states. By carefully controlling these electrical parameters, the system can program intermediate resistance states with sufficient precision for MLC operation, overcoming the manufacturing precision challenges while preserving the scalability benefits of 1S1R structures
3Quantity of substance
If voltage pulses are applied to tune PCM cell into intermediate states, then storage capacity is improved with n bits per cell, but energy consumption increases
Solution Approach 1:
The patent uses periodic voltage pulse sequences to program the phase change material into different resistance states. By applying multiple pulses with decreasing amplitudes or specific timing patterns, the system can achieve intermediate states that enable multi-bit storage per cell. The periodic nature of these pulses allows precise control of the phase change process while managing energy consumption through optimized pulse durations and intervals
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The MLC 1S1R structure achieves high-density data storage with n bits per cell, providing 2n cell states, such as 4 or 16 states, by controlling the PCM cell's resistance levels through carefully designed voltage pulses, enhancing scalability and reducing costs compared to traditional transistor-based systems.
Implementation Method 1
The temperature of the phase change material can be varied to selectively change the phase of the PCM between a crystalline state and an amorphous state
Implementation Method 2
The current flowing through the PCM increases the temperature phase change material, thereby invoking the crystalline state or an amorphous state
Implementation Method 3
A multi-level cell (MLC) 1S1R structure is implemented using a stacked arrangement of a phase change memory (PCM) cell and a chalcogenide-based ovonic threshold switch (OTS) selector, allowing for voltage pulses to tune the PCM cell into fully set, fully reset, or intermediate states
Data Source
AI summary
A multi-level cell (MLC) one-selector-one-resistor (1S1R) three-dimensional (3D) cross-point memory system includes at least one MLC 1S1R structure including a stacked arrangement of a phase change memory (PCM) cell and a threshold switch selector. An electrically conductive bit line is in electrical communication with the OTS selector, and an electrically conductive word line is in electrical communication with the PCM cell. A controller is in electrical communication with the bit line and the word line. The controller is configured to select at least one voltage pulse from a group of different voltage pulses comprising a read pulse, a partial set pulse, a set pulse, a partial reset pulse, and a reset pulse, and configured to deliver the selected at least one voltage pulse to the at least one MLC 1S1R structure.