Multi-Level Cell Storage Using Audit Bits for Reliability
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Solution Overview
Problem
Multi-level cell solid-state storage devices face reduced longevity and error rates due to increased capacity demands, leading to decreased reliability, especially under high temperature conditions and power loss, which is not effectively addressed by existing technologies.
Innovation Solution
Implementing a method that uses multi-level memory cells with audit bits to validate data integrity by reading audit bits separately or concurrently with data bits, flipping suspect data bits, and marking cells as unreliable if error thresholds are exceeded, effectively converting the storage device to operate as single-level cell storage when reliability decreases.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multi-level cell solid-state storage is used to increase capacity, then storage capacity increases, but reliability and longevity decrease
Solution Approach 1:
The patent segments the multi-level cell storage into two distinct functional parts: data bits for storage and audit bits for validation. Each bit position is independently managed, with audit bits separately verifying data integrity. This segmentation allows the system to maintain high capacity through multi-level cells while improving reliability through dedicated validation mechanisms.
Solution Approach 2:
The patent introduces audit bits as intermediary elements that mediate between the stored data and the verification process. These audit bits act as a buffer or mediator that can detect and report errors without directly affecting the stored data, thereby enhancing reliability while preserving the high-capacity multi-level cell structure.
2Ease of manufacture
If multi-level cell storage operates at high capacity, then cost per bit decreases, but error rates increase
Solution Approach 1:
The patent implements a self-service mechanism where the storage system automatically generates and uses audit bits to detect and correct errors. This self-verification capability allows the system to maintain high capacity and low cost while compensating for increased error rates through automated error detection and correction, reducing the need for expensive redundant hardware.
3Reliability
If audit bits are read separately from data bits, then data integrity verification improves, but access time increases
Solution Approach 1:
The patent merges the reading of data bits and audit bits into a unified process. By combining these operations, the system verifies data integrity without requiring separate access cycles, thereby maintaining improved data integrity verification while minimizing the increase in access time through consolidated read operations.
Data Source
AI summary
An apparatus, system, and method are disclosed for storing information in a storage device that includes multi-level memory cells. The method involves storing data that is written to the storage device in the LSBs of the multi-level memory cells, and storing audit data in the MSBs of the multi-level memory cells. The audit data can be read separately from the data and used to determine whether or not there has been any unintended drift between states in the multi-level cells. The audit data may be used to correct data when the errors in the data are too numerous to be corrected using error correction code (ECC). The audit data may also be used to monitor the general health of the storage device. The monitoring process may run as a background process on the storage device. The storage device may transition the multi-level memory cells to operate as single-level memory cells.