MLC Chip Error Rate Analysis at Data Block and Page Levels
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Solution Overview
Problem
Current methods for analyzing error rates in MLC chips, such as the single-bit global analysis method, are inadequate as they cannot effectively assess error rates at the data block and page levels, hindering comprehensive performance evaluation of MLC chips.
Innovation Solution
A method, system, and device for analyzing error rates in MLC chips by selecting data blocks, performing erasing-writing operations, reading dual-bit states, and calculating error rates for both pages and blocks, allowing for detailed analysis of performance based on first and second error rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If single-bit global analysis method is used, then analysis process is simple, but cannot effectively assess error rates at data block and page levels
Solution Approach 1:
The patent segments the error rate analysis into multiple levels: chip level, data block level, and page level. By dividing the analysis into these distinct segments, the system can provide precise measurements at each level while maintaining operational simplicity through automated multi-level processing. This segmentation resolves the contradiction by enabling detailed assessment without complicating the overall analysis process.
Solution Approach 2:
The patent introduces multiple analysis dimensions beyond the traditional single-bit global approach. It adds data block-level and page-level dimensions to the error rate analysis, transforming a one-dimensional analysis into a multi-dimensional framework. This dimensional expansion enables comprehensive assessment of error rates at different granularities while maintaining systematic simplicity through structured processing.
2Reliability
If comprehensive multi-level error rate analysis is implemented, then performance evaluation completeness is improved, but analysis complexity increases
Solution Approach 1:
The patent designs a universal error rate analysis system that can perform multiple functions: chip-level error rate calculation, data block-level error rate calculation, and page-level error rate calculation. This multi-functional design allows a single system to provide comprehensive performance evaluation without requiring separate analysis tools for each level, thereby reducing overall system complexity while improving evaluation completeness.
Solution Approach 2:
The patent implements feedback mechanisms where error rates at different levels (data block and page) feed back into the overall chip-level error rate assessment. This feedback loop enables comprehensive performance evaluation by continuously monitoring and integrating error rates across all levels, while the automated feedback processing reduces manual analysis complexity and improves system efficiency.
Data Source
AI summary
A method, system and device for analyzing an error rate of an MLC chip. The method includes selecting data blocks from the MLC chip, and performing erasing-writing operations to the data blocks; after the erasing-writing operations are completed, reading each of groups of the dual-bits corresponding to each of the first pages and the second pages of the data blocks, and determining the bit state of the each of groups of the dual-bits; counting up the first total quantity of all of the dual-bits corresponding to the target page in the target bit state representing that the data writing is erroneous, to obtain a first error rate of the target page in the target bit state; and counting up a second total quantity of all of the dual-bits corresponding to the data blocks in the target bit state.