MLC Codeword Error Correction Power Reduction
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Solution Overview
Problem
Existing memory systems face challenges in efficiently programming memory cells to intermediate voltage regions without overlapping with high or low voltage regions, leading to errors in data retrieval due to threshold voltage drift over time and environmental factors.
Innovation Solution
A memory sub-system with a programming manager that uses counter-controlled programming pulses and bitline/wordline drivers to dynamically adjust voltage pulses, allowing memory cells to be programmed into precise intermediate voltage regions, and employs error correction codes to recover data from errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are programmed to intermediate voltage regions to increase storage capacity, then storage density is improved, but error rate increases due to threshold voltage drift
Solution Approach 1:
The patent divides the voltage region into multiple discrete levels (intermediate voltage regions between low and high voltage regions) to store additional bits per cell. By segmenting the voltage spectrum into distinct programmable levels, the system increases storage capacity while maintaining readable distinctions between states, thereby achieving higher density without completely sacrificing reliability through the use of ECC.
Solution Approach 2:
The patent applies error correction codes during the programming process to preemptively correct potential errors before they occur during read operations. By performing error correction in advance (during programming rather than only during reading), the system compensates for the increased error susceptibility of intermediate voltage regions, thus maintaining reliability while utilizing multi-level storage.
2Manufacturing precision
If counter-controlled programming pulses are used to achieve precise voltage control, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The patent employs counter-controlled programming pulses that incrementally adjust voltage levels based on feedback from read operations. The counter tracks the number of pulses applied and adjusts subsequent programming attempts accordingly, creating a closed-loop control system that achieves precise voltage positioning without requiring overly complex external control circuitry.
Solution Approach 2:
The programming process uses periodic pulse sequences with controlled frequencies and durations to gradually shift memory cell voltages to target intermediate regions. By applying voltage adjustments in regular, repeatable cycles rather than continuous analog control, the system achieves precision through digital timing control, simplifying the overall device architecture while maintaining accurate voltage positioning.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables accurate programming of memory cells into intermediate voltage regions, reducing errors and maintaining data integrity over time, while also correcting errors through efficient ECC mechanisms.
Implementation Method 1
A programming manager is configured to sense a state of the memory cell and determine whether the memory cell is to be programmed to a low voltage region, an intermediate voltage region, or a high voltage region based on the state of the memory cell
Implementation Method 2
In response to determining that the memory cell is to be programmed to the intermediate voltage region, a number of programming pulses is applied to the memory cell to program the memory cell to the intermediate voltage region
Data Source
AI summary
In some aspects, the techniques described herein relate to a method including: selecting a plurality of coding tables, the plurality of coding tables including an encoding table and a decoding table; building an error table using the plurality of coding tables, the error table representing potential bit errors that may occur during reading and writing to a memory device using the plurality of coding tables; masking the error table to eliminate error values in the error table meeting a preconfigured condition; determining if the error table includes one or more errors in invalid positions; and storing the error table when the error table does not include one or more errors in invalid positions.