Multi-Level Cell Copyback Program Method with Selective Verifying
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Solution Overview
Problem
Multi-level cell (MLC) non-volatile memory devices face challenges in data copyback operations, particularly in amending damaged data and performing unified verifying operations for LSB and MSB program operations, which complicates the threshold voltage distribution and requires distinct algorithms compared to single-level cell (SLC) devices.
Innovation Solution
A multi-level cell copyback method that involves reading LSB data, storing it in a page buffer, amending the data through a data inputting circuit, and programming it to a target page, while performing selective verifying operations based on different verifying voltages to ensure accurate data transfer and storage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multi-level cell (MLC) structure is used to store two data in one memory cell, then data processing capacity is improved, but driving method becomes complicated compared to single-level cell (SLC)
Solution Approach 1:
The patent segments the data storage into LSB (least significant bit) and MSB (most significant bit) components, allowing independent reading and programming operations. This segmentation enables complex MLC data to be handled through simpler, standardized operations for each bit component, reducing overall driving complexity while maintaining high data processing capacity.
Solution Approach 2:
The patent introduces a page buffer as an intermediary component between the memory cell array and external data storage. The page buffer temporarily stores read data and provides a staging area for write operations, simplifying the driving method by providing a buffer zone that mediates between the complex MLC structure and simpler external interfaces.
2Ease of operation
If copyback operation is performed to transfer data between memory cells, then data can be amended, but damaged data may occur during the process
Solution Approach 1:
The patent performs preliminary reading of the source page data before the copyback operation, storing it in the page buffer. This preliminary action allows the system to have a complete copy of the source data ready, so that if damage occurs during transfer, the original undamaged data can be restored from the buffer, ensuring data integrity while maintaining ease of operation.
Solution Approach 2:
The patent creates a cushioning mechanism by storing read data in the page buffer before programming it back to the memory cell array. This beforehand cushioning provides a safety margin - if the copyback process fails or data becomes damaged, the buffer contains the original undamaged data that can be used for recovery, thus protecting data integrity during the amendment operation.
3Measurement precision
If separate verifying operations are performed for LSB and MSB program operations, then data accuracy can be ensured, but device area and control complexity increase
Solution Approach 1:
The patent merges the verifying operations for LSB and MSB program operations into a single unified verifying operation. Instead of requiring separate verification circuits and operations for each bit component, the system performs one verification operation that checks both LSB and MSB data, thereby ensuring data accuracy while reducing the area required for ROM and control circuits.
Solution Approach 2:
The patent creates a universal verifying operation that serves multiple functions - it verifies both LSB and MSB program operations using the same verification circuitry and process. This multi-functionality allows a single verification mechanism to handle all data accuracy checks, eliminating the need for separate specialized verification circuits for each bit component and thus reducing overall device area.
Data Source
AI summary
A multi-level cell copyback program method in a non-volatile memory device is disclosed. The method includes performing a multi-level cell copyback program operation; performing selectively a first verifying operation, a second verifying operation or a third verifying operation in accordance with data stored in an MSB node of the first register or data stored in an LSB node of the second register. The first verifying operation is based on a first verifying voltage. The second verifying operation is based on a second verifying voltage higher than the first verifying voltage. And the third verifying operation is based on a third verifying voltage higher than the second verifying voltage. The copy back program operation is performed repeatedly in accordance with result of the verifying operation.