Multi-Level Cell ECC Storage Based on Cell Error Rates
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Solution Overview
Problem
Traditional solid-state memory devices face inefficiencies in programming and reading operations due to their binary nature, which becomes cumbersome as more bits are stored per cell, leading to longer operation times and increased susceptibility to errors as bit storage capacity increases.
Innovation Solution
The memory devices utilize multi-level cells (MLCs) that store data as threshold voltage ranges, allowing for single read and write operations to represent complete bit patterns rather than individual bits, and employ a calibration method to adjust bit levels based on error rates for reliable storage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple bits are stored on each multi-level cell, then storage capacity is improved, but operation time increases
Solution Approach 1:
The patent combines multiple bit operations into a single read/write operation by treating the multi-level cell as a unified entity that stores and retrieves complete bit patterns simultaneously. Instead of sequentially accessing individual bits, the system performs parallel operations on all bits stored in the cell, merging what would traditionally be separate operations into one atomic action.
Solution Approach 2:
The patent transitions from binary (2-state) memory operations to multi-level (analog) memory operations by utilizing threshold voltage ranges instead of discrete voltage levels. This dimensional change from digital to analog representation allows multiple data values to be encoded in a continuous parameter space, enabling simultaneous access to multiple bits through a single operation.
2Quantity of substance
If multiple bits are stored on each multi-level cell, then storage capacity is improved, but error susceptibility increases
Solution Approach 1:
The patent changes the fundamental parameter used for data storage from discrete binary voltage levels to continuous threshold voltage ranges. By mapping multiple bits to an analog parameter (threshold voltage) that can assume any value within a range, the system increases the information density per cell while maintaining reliability through the continuous nature of the parameter, which provides inherent noise margin and error tolerance.
3Device complexity
If binary operations are used for each bit, then simplicity is maintained, but operation efficiency decreases
Solution Approach 1:
The patent merges multiple sequential binary operations into a single parallel operation by treating the multi-level cell as a unified data structure. The read and write operations simultaneously handle all bits stored in the cell, eliminating the need for repeated sequential accesses and dramatically improving throughput while maintaining operational simplicity through unified interface protocols.
Solution Approach 2:
The patent creates a universal operation mode that handles multiple bits simultaneously, making the memory system multi-functional in terms of data width. The same read/write circuitry and control logic that would handle single-bit operations are extended to handle multi-bit patterns in a unified manner, achieving both simplicity and efficiency through a single versatile operation type.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces operation times and enhances reliability by enabling single analog signals to represent multiple bits, improving storage efficiency and error correction capabilities, particularly in high-capacity memory applications.
Implementation Method 1
The memory devices utilize threshold voltage ranges to represent multiple data values, allowing for single read and write operations that handle complete bit patterns rather than individual bits
Data Source
AI summary
Memory devices that, in a particular embodiment, receive and transmit analog data signals representative of bit patterns of two or more bits such as to facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits. Programming error correction code (ECC) and metadata into such memory devices includes storing the ECC and metadata at different bit levels per cell based on an actual error rate of the cells. The ECC and metadata can be stored with the data block at a different bit level than the data block. If the area of memory in which the block of data is stored does not support the desired reliability for the ECC and metadata at a particular bit level, the ECC and metadata can be stored in other areas of the memory array at different bit levels.