Multi-Level Cell Flash Memory Programming Order Flexibility
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Solution Overview
Problem
Conventional multi-level cell (MLC) flash memory devices are limited by an ordering constraint that prohibits programming the most significant bit (MSB) after the least significant bit (LSB), restricting true random access and affecting overall system performance.
Innovation Solution
A method and apparatus that allow programming of MLCs in arbitrary order by determining whether to program the upper or lower bit, detecting the current logic state, generating and applying program and verify voltages to a word line connected to the selected memory cell, enabling programming from state '10' to '00' by either bit, and using a voltage generator, sense amplifier, write driver, and program controller to control the programming sequence.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the LSB is programmed before the MSB in conventional MLC flash memory, then the programming operation can be performed favorably according to the state transition diagram, but the ordering constraint prohibits true random access and restricts system performance
Solution Approach 1:
The patent inverts the conventional programming sequence by allowing the MSB to be programmed before the LSB. This is achieved by modifying the state transition diagram to include valid paths for MSB-first programming (paths 10, 11, 12, 13), thereby eliminating the ordering constraint while maintaining programming reliability through proper threshold voltage transitions in both directions.
Solution Approach 2:
The patent introduces dynamic programming sequence selection where the system can adaptively choose between LSB-first or MSB-first programming paths based on the current state of the memory cell and system requirements. This dynamic approach enables true random access while maintaining reliable programming operations through flexible state transition paths.
2Device complexity
If the ordering constraint is enforced in conventional MLC flash memory, then the programming sequence is simplified, but true random access is prohibited and system performance is affected
Solution Approach 1:
The patent segments the programming operation into independent bit-level transitions, allowing either bit to be programmed first without affecting the other. By dividing the programming process into separate LSB and MSB programming paths with appropriate threshold voltage transitions, the system achieves simplified control logic while enabling random access and improved performance.
Solution Approach 2:
The patent changes the programming sequence parameter from fixed (LSB before MSB) to variable (either bit first). This is achieved by modifying the state transition diagram to accommodate multiple valid programming paths, allowing the system to select the optimal sequence based on current cell state and performance requirements, thereby improving productivity while maintaining manageable complexity.
Data Source
AI summary
A method of programming a selected cell in a multi-level flash memory device comprises determining whether to program an upper bit or a lower bit of a selected memory cell, detecting a current logic state of two bits of data stored in the selected memory cell, determining a target logic state for the upper or lower bit, generating a program voltage and a verify voltage for programming the upper or lower bit to the target logic state, and applying the program voltage and the verify voltage to a word line connected to the selected memory cell.