MLC Flash Memory Program Verify Using Selective Bitline Precharge
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Solution Overview
Problem
Existing program verify techniques for multi-level cell (MLC) flash memory devices are inefficient due to significant RC delay and undesired SRC bounce voltage bias, which increase page programming time and affect data integrity.
Innovation Solution
Implementing a method that selectively precharges only target bitlines during program verify operations, avoiding precharge of non-target bitlines to minimize SRC bounce voltage bias and reduce RC delay, thereby optimizing the programming process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If all bitlines are precharged during program verify operations, then data integrity can be maintained, but RC delay increases and page programming time is extended
Solution Approach 1:
The patent segments the bitlines into target bitlines (corresponding to target memory cells) and non-target bitlines (corresponding to non-target memory cells). During program verify operations, only the target bitlines are precharged while non-target bitlines remain unprecharged. This segmentation allows the system to maintain data integrity for verified cells without incurring the RC delay penalty of precharging all bitlines, thereby reducing overall page programming time.
Solution Approach 2:
The patent applies local quality by providing different treatment to different parts of the bitline structure. Target bitlines receive precharge treatment to ensure proper verification of target memory cells, while non-target bitlines are deliberately excluded from precharging to minimize unnecessary RC delay. This differentiated approach optimizes the verification process for relevant cells while avoiding the time penalty of global precharge operations.
2Reliability
If all bitlines are precharged during program verify operations, then verification coverage is complete, but SRC bounce voltage bias is introduced
Solution Approach 1:
The patent segments bitlines into target and non-target categories based on their corresponding memory cells. By precharging only target bitlines and excluding non-target bitlines from the precharge operation, the system achieves sufficient verification coverage for the intended memory cells while preventing the SRC bounce voltage bias that would result from precharging all bitlines. This segmentation strategy isolates the harmful effect to non-target bitlines that remain unprecharged.
Solution Approach 2:
The patent extracts non-target bitlines from the precharge operation, deliberately excluding them from the verification process. This extraction removes the source of SRC bounce voltage bias while maintaining verification coverage for target memory cells. The non-target bitlines are taken out of the precharge sequence, eliminating their harmful electrical contribution while preserving the integrity of target cell verification.
3Reliability
If conventional program verify techniques are used, then data persistence is ensured, but power consumption is not optimized
Solution Approach 1:
The patent segments the bitline precharge operation to apply power only where necessary. By precharging only target bitlines corresponding to target memory cells and leaving non-target bitlines unprecharged, the system reduces overall power consumption during verification operations. This segmentation approach maintains data persistence through targeted verification while eliminating unnecessary power consumption associated with global precharge operations.
Solution Approach 2:
The patent applies partial action by performing precharge operations only on the subset of bitlines needed for verification (target bitlines) rather than the complete set (all bitlines). This partial precharge approach is sufficient to ensure data persistence for verified cells while avoiding the excessive power consumption that would result from precharging all bitlines, including those not involved in the verification process.
Data Source
AI summary
A disclosed example includes generating a first binary value corresponding to a first sensed threshold voltage of a multi-level cell (MLC) memory cell corresponding to a first time at which a bias voltage is applied to a temporary bias cache capacitor of the MLC memory cell; generating a second binary value corresponding to a second sensed threshold voltage of the MLC memory cell corresponding to a second time at which the bias voltage is not applied to the temporary bias cache capacitor of the MLC memory cell; and based on the first and second binary values, selecting whether to program the MLC memory cell using a full program pulse or a partial program pulse.