MLC Flash Memory LDPC Post-Processing for Burst Error Correction
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Solution Overview
Problem
Multilevel cell (MLC) flash memory devices in portable memory devices face increased error rates, which traditional error correction mechanisms struggle to manage effectively, leading to burst errors and instability issues.
Innovation Solution
A memory device controller with a processing circuit and data protection circuit that encodes data using a parity-check matrix and performs post-processing to generate a parity-check code, allowing for error correction and reduced error rates without significantly increasing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If MLC flash memory is used to increase storage capacity and reduce cost, then storage density and cost-effectiveness are improved, but error rate increases leading to burst errors
Solution Approach 1:
The patent segments the error correction process into two distinct stages: first, a primary error correction mechanism corrects standard errors, and second, a specialized burst error correction mechanism handles remaining burst errors. This segmentation allows the system to address different error types with appropriate correction strengths, effectively managing the high error rates inherent in MLC flash memory while maintaining storage capacity.
Solution Approach 2:
The patent employs a composite error correction approach by combining multiple correction mechanisms (primary error correction + burst error correction) into a unified system. This composite structure enables the memory device to handle both standard bit errors and burst errors that occur in MLC flash memory, thereby improving overall reliability without sacrificing storage density.
2Device complexity
If traditional error correction mechanisms are used in MLC flash memory, then implementation complexity is kept low, but they fail to deal with burst errors effectively
Solution Approach 1:
The patent implements a dynamic error correction system that adapts its correction strategy based on the detected error pattern. The system first attempts standard error correction, then dynamically switches to burst error correction mode when burst errors are detected. This dynamic approach allows the system to maintain low complexity for normal operations while providing robust burst error correction when needed.
Solution Approach 2:
The patent changes the correction parameters based on error characteristics. For standard errors, conventional correction parameters are used, but when burst errors are detected, the system adjusts parameters to activate specialized burst error correction algorithms. This parameter adaptation enables effective burst error handling without permanently increasing system complexity.
3Reliability
If advanced error correction mechanisms are implemented to reduce error rates, then data reliability is improved, but manufacturing cost and device complexity increase
Solution Approach 1:
The patent performs preliminary error correction in a first stage before final data retrieval. By pre-correcting errors during the write operation or immediately upon detection, the system reduces the burden on subsequent correction stages. This preliminary action allows advanced error correction to be implemented without proportionally increasing overall system complexity.
Solution Approach 2:
The patent introduces an intermediary error correction layer that sits between the raw MLC flash memory and the data processing logic. This intermediary component handles the complex error correction tasks, isolating the complexity from the main controller and allowing standard processing logic to remain simple while still achieving high reliability through the intermediary correction mechanism.
Data Source
AI summary
A method for performing data management in a memory device includes: receiving a set of data from a host device positioned outside the memory device; encoding the set of data according to a first sub-matrix of a predetermined parity-check matrix to generate a partial parity-check code; performing post-processing upon the partial parity-check code according to a predetermined post-processing matrix to generate a parity-check code of the set of data, where the predetermined post-processing matrix is not equivalent to any inverse matrix of a transpose matrix of a second sub-matrix of the predetermined parity-check matrix; and writing/programming a codeword of the set of data into a non-volatile memory of the memory device to allow the memory device to perform error correction when reading the set of data from the non-volatile memory. An associated memory device and a controller thereof are also provided.