MLC Flash Data Layout for Early-Stop Error Correction
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Solution Overview
Problem
Existing Multi-Level Cell Flash memory devices face inefficiencies in processing time and power consumption due to the need for comprehensive error correction across all data bits, which can be optimized by strategically interleaving data across bit-pages based on error probability.
Innovation Solution
The method involves interleaving data such that the first portion with the highest error probability is stored in the LSB bit-page, the second portion in the LSB+1 bit-page, and the last portion in the MSB bit-page, allowing for early detection and correction of errors, thereby reducing the need for full codeword scanning and minimizing processing time and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If comprehensive error correction is applied to all data bits in MLC flash memory, then error detection and correction reliability is improved, but processing time and power consumption increase
Solution Approach 1:
The patent segments the codeword into multiple portions and applies error correction processing to each portion sequentially rather than processing all bits comprehensively. This segmentation allows the system to stop processing once all errors are detected and corrected, reducing unnecessary processing time while maintaining reliability.
Solution Approach 2:
The patent implements partial error correction action by processing only the necessary portions of the codeword. The error correction process stops as soon as all errors are detected and corrected, avoiding excessive processing of remaining error-free portions, thus reducing processing time while maintaining complete error correction capability.
2Reliability
If comprehensive error correction is applied to all data bits in MLC flash memory, then error detection and correction reliability is improved, but power consumption increases
Solution Approach 1:
The patent segments the error correction process into multiple portions that are processed sequentially. This segmentation enables the system to consume less power by stopping processing once errors are corrected, avoiding continuous power consumption that would occur with comprehensive processing of all data bits.
Solution Approach 2:
The patent applies partial error correction action by processing only the necessary portions of the codeword until all errors are detected and corrected. This prevents excessive power consumption that would result from continuing to process all remaining bits even after errors are already corrected.
3Ease of manufacture
If data is stored without strategic interleaving across bit-pages, then storage simplicity is maintained, but error distribution and ECC performance deteriorate
Solution Approach 1:
The patent applies preliminary interleaving action during the data writing phase, strategically distributing data portions across different bit-pages before storage. This preliminary arrangement ensures optimal error distribution and ECC performance without adding complexity to the storage structure itself, as the interleaving is applied to the logical address mapping rather than the physical storage architecture.
Data Source
AI summary
A method of storing data includes storing a first portion of data in bit positions of a non-volatile memory having a first probability of error; storing a second portion of the data in bit positions of the non-volatile memory having a second probability of error, wherein the second probability of error is lower than the first probability of error; storing error correction parity bits with the data; and applying an error correction scheme to read data using the error correction parity bits, wherein at least one bit of the first portion is checked for correction before any bit of the second portion is checked for correction. The error correction scheme is stopped before checking for correcting of all the data.