MLC Flash Memory ECC Layout Without Dedicated Parity Area
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Solution Overview
Problem
Conventional flash memories face challenges in reducing memory size and simplifying controller operation, particularly for Multi-Level Cell (MLC) flash devices, which require costly redesigns due to fixed ECC configurations and inefficient use of memory space, leading to higher costs and potential performance mismatches.
Innovation Solution
The method involves encoding data bits to generate parity bits and programming multi-state memory cells to represent both data and parity bits, allowing each cell to be programmed to multiple states without a dedicated parity area, thereby optimizing memory usage and flexibility in ECC configuration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dedicated parity cells are used for error correction, then data reliability is improved, but memory array size increases
Solution Approach 1:
The patent merges data bits and parity bits into the same memory cells for storage. Instead of using separate dedicated parity cells, the system encodes data bits to generate parity bits and stores both types of bits together in the same memory array, eliminating the need for separate parity storage area while maintaining error correction capability
Solution Approach 2:
The memory cells are designed to serve multiple functions: they can store both data bits and parity bits interchangeably. The same memory cells that store user data also store the generated parity bits, making the storage system more efficient by eliminating dedicated parity areas
2Ease of manufacture
If fixed ECC configuration is used, then manufacturing process is simplified, but adaptability to different memory sizes is reduced
Solution Approach 1:
The patent implements dynamic ECC configuration where the number of parity bits can be adjusted based on the actual memory array size and data requirements. The system allows flexible selection of ECC parameters (such as code rate) to match different memory capacities and performance requirements, rather than being locked into a fixed configuration
Solution Approach 2:
The system enables changing of ECC parameters including code rate, block size, and number of parity bits to adapt to different memory array sizes and application requirements. This parameter flexibility allows the same memory device to be optimized for different capacities and performance levels without requiring physical redesign
3Reliability
If more redundancy bits are added, then error correction capability is improved, but information bits per cell decreases
Solution Approach 1:
The patent employs variable code rate ECC where the ratio of data bits to parity bits can be adjusted according to the required error correction capability. By dynamically changing the code rate parameter, the system can optimize the balance between redundancy overhead and information storage capacity based on specific application needs
Data Source
AI summary
A method and system for optimizing flash memory without dedicated parity area and with reduced array size. The memory size of a multi level cell (MLC) flash is reduced and controller operation is simplified. Simplified operation includes the controller being able to program each host data page to an integer number of flash pages. A maximal available information bits per cell (IBPC) is maintained in a flash device while also maximizing the programming throughput of the flash. Features include the ability to dynamically select which number of cell states is used by flash memory cells.