MLC NAND Flash ECC Pairing for Upper-Lower Page Error Imbalance
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Solution Overview
Problem
Current Multi-Level Cell (MLC) NAND flash memory systems face inefficiencies due to unequal bit error rates between upper and lower pages, where the same error correction coding (ECC) is used for both, leading to over-protection for lower pages and underutilization of ECC power on upper pages, resulting in reduced storage system reliability.
Innovation Solution
The solution involves pairing lower and upper pages, either within the same block, different flash dies, or different flash channels, to compute and apply split error correcting codes (ECC) specifically for each segment, allowing for more effective error correction and increased ECC effectiveness at a lower code rate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the same error correction coding (ECC) is used for both upper and lower pages, then the implementation is simple and uniform, but the ECC power is underutilized on upper pages and over-protection is applied to lower pages, reducing storage system reliability
Solution Approach 1:
The patent segments the ECC protection into separate codes for upper and lower pages. Specifically, it generates a first ECC code for the upper page and a second ECC code for the lower page, allowing each page to receive error correction protection optimized for its specific error characteristics. This segmentation resolves the contradiction by enabling differentiated protection strategies while maintaining implementation simplicity through the use of separate but parallel ECC code generation processes.
Solution Approach 2:
The patent applies local quality by tailoring the ECC protection to the specific error characteristics of each page. Upper pages, which have higher error rates, receive stronger error correction capability through the first ECC code, while lower pages receive appropriate protection through the second ECC code. This localized optimization of error correction strength according to actual error distribution resolves the contradiction between reliability and complexity by avoiding both over-protection and under-protection.
2Reliability
If stronger ECC protection is applied to upper pages with higher error rates, then error correction effectiveness improves, but the code rate increases and storage efficiency decreases
Solution Approach 1:
The patent applies partial action by providing differentiated ECC protection only where needed. The first ECC code for upper pages is designed with appropriate strength to handle the higher error rates, while the second ECC code for lower pages uses a different code rate optimized for their lower error characteristics. This partial optimization approach resolves the contradiction by applying stronger protection only to upper pages where it is most needed, rather than uniformly increasing protection across all data.
Solution Approach 2:
The patent changes the ECC parameters (code rate, code length) to match the specific error characteristics of each page type. By adjusting these parameters based on empirical error rate measurements for upper versus lower pages, the system achieves optimal error correction effectiveness without unnecessarily increasing the overall code rate. This parameter optimization resolves the contradiction by matching protection strength to actual error conditions rather than applying a one-size-fits-all approach.
Data Source
AI summary
A memory system includes a flash subsystem for storing data identified by page numbers. The memory system further includes a central processing unit (CPU), and a flash controller coupled to the CPU, the CPU being operable to pair a lower with an upper page. Further included in the memory system is a buffer including a page of data to be programmed in a block of the flash subsystem, wherein split segments of pages are formed and concatenated with split error correcting code (ECC), the ECC having a code rate associated therewith.