Adaptive Error Correction for Multi-Level Cell Flash Memory
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Solution Overview
Problem
Conventional error correction methods for flash memory in enterprise storage environments are inefficient in achieving low uncorrectable bit error rates over the total service life and traffic loads, particularly in solid-state drives (SSDs) using multi-level cell (MLC) flash memory, leading to reliability and performance issues.
Innovation Solution
The solution involves grouping flash pages across multiple dies and implementing a redundant error correction scheme that includes journaling cell slots for user data and grid parity data, allowing for adaptive selection of error correction codes and efficient data storage and retrieval, enabling seamless operation despite die failures and reducing overprovisioning, power consumption, and endurance impacts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional error correction methods are used for MLC flash memory, then device complexity is reduced, but uncorrectable bit error rates increase and reliability deteriorates
Solution Approach 1:
The patent segments the flash memory into multiple independent page stripes, each with its own error correction code. This segmentation allows the system to isolate errors to specific page stripes and apply targeted correction, improving overall reliability without requiring a monolithic complex error correction system. Each page stripe can be independently managed and corrected.
Solution Approach 2:
The patent introduces a two-dimensional error correction architecture where page stripes are arranged in a grid structure with row and column dimensions. This dimensional organization enables cross-page stripe error correction, allowing errors to be corrected by combining information from multiple page stripes. This approach significantly reduces uncorrectable bit error rates while maintaining manageable device complexity through structured organization.
2Ease of manufacture
If MLC flash memory is used to reduce cost, then manufacturing cost decreases, but program/erase cycle lifetime and signal-to-noise ratio deteriorate
Solution Approach 1:
The patent implements beforehand cushioning by storing multiple copies of the same data across different page stripes before any failure occurs. This redundant storage strategy ensures that even if some page stripes fail due to limited program/erase cycle lifetime, the data remains accessible through other copies. This approach extends the effective operational life of MLC flash memory while maintaining cost-effectiveness.
Solution Approach 2:
The patent dynamically adjusts error correction parameters and data distribution strategies based on the degradation state of MLC flash memory. As program/erase cycles increase and signal-to-noise ratio deteriorates, the system adapts by strengthening error correction for affected page stripes and redistributing data to healthier regions. This parameter adaptation extends the usable lifetime of MLC devices.
3Reliability
If redundant error correction schemes are implemented across multiple page stripes, then reliability improves, but device complexity and overhead increase
Solution Approach 1:
The patent implements universal error correction mechanisms that can operate across multiple page stripes simultaneously. The same error correction code and decoding algorithms are applied uniformly to all page stripes in the grid, reducing the need for separate complex correction systems for each stripe. This multi-functional approach improves reliability through redundancy while controlling device complexity by reusing the same correction infrastructure.
Data Source
AI summary
Apparatus and methods provide relatively low uncorrectable bit error rates, low write amplification, long life, fast and efficient retrieval, and efficient storage density such that a solid-state drive (SSD) can be reliably implemented using various types of memory cells, including relatively inexpensive multi-level cell flash. One embodiment intelligently coordinates remapping of bad blocks with error correction code control, which eliminates the tables used to avoid bad blocks.