Multilevel Cell Flash Memory Paired Page Programming
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Solution Overview
Problem
Multilevel cell (MLC) flash memory technology faces challenges in reliably programming upper-level pages without damaging pre-written data on lower levels, leading to data loss and instability, especially in power outages, and existing solutions either compromise on durability or reduce memory capacity.
Innovation Solution
A method that programs paired pages with the same data bits, using a pairing table to combine lower and upper pages, and employs a buffer block mechanism to ensure data integrity during power outages, increasing the error interval and durability beyond single-level cell (SLC) standards.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multilevel cells are used to increase storage capacity, then memory capacity is improved, but data retention stability deteriorates
Solution Approach 1:
The patent divides the memory into separately erasable physical blocks, each containing multiple pages. This segmentation allows independent programming of lower and upper pages, enabling the lower page to be programmed first with data, then the upper page to be programmed with the same data to create a paired page structure. This segmentation approach maintains high storage capacity through MLC while improving data retention by ensuring both pages contain identical data for verification.
Solution Approach 2:
The patent implements preliminary programming of the lower page before programming the upper page. The lower page is programmed first and then used as a reference template for programming the upper page with the same data. This preliminary action ensures that the lower page data is firmly established before the upper page is programmed, preventing data loss and improving overall data retention stability.
2Quantity of substance
If upper pages are programmed to increase storage capacity, then memory capacity is improved, but data integrity deteriorates
Solution Approach 1:
The patent uses the lower page as a template or copy reference when programming the upper page. The upper page is programmed with the same data as the lower page, creating a paired page structure where both pages contain identical data. This copying approach ensures data integrity by verifying that both pages contain the same information, preventing data loss even during power outages or programming errors.
3Reliability
If paired pages are programmed with the same data to improve reliability, then data retention is improved, but programming time increases
Solution Approach 1:
The lower page is programmed first as a preliminary action, then the upper page is programmed with the same data using the lower page as a reference. This sequential preliminary action allows the system to establish the lower page data firmly before copying it to the upper page, improving reliability while minimizing the time required for the pairing operation.
4Reliability
If error interval is increased to improve data retention, then data retention is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent uses the lower page as a precise copy template for programming the upper page. By copying the same data from the lower page to the upper page, the system ensures that both pages have identical data patterns, which maximizes the error interval and improves data retention. This copying approach reduces the impact of manufacturing variations in threshold values.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method provides reliable storage with increased durability and reduced wear, ensuring data integrity even during power outages by doubling the programming charge and using a buffer block to maintain data consistency, outperforming SLC technology in data retention and reducing memory wear.
Implementation Method 1
Electron migration means that the charge can be reduced and the interval from the next lowest threshold value can decrease
Data Source
AI summary
Data bits are programmed in cells of a flash memory which is divided into a multiplicity of separately erasable physical blocks, which are in turn split into individual physical pages to which the data bits can be written. The data bits are held in multilevel cells that store one lower bit and one upper bit per cell. The four states of which are distinguished by three voltage threshold values. The lower states are associated with the lower bit and the upper states are associated with the upper bit. The pages are distinguished by lower pages allocated to the lower bits, and upper pages allocated to the upper bits. Lower and upper pages which contain the same cells are combined by a pairing table to form paired pages. Reliable storage of data bits is achieved by programming paired pages with the same data bits and listing them as reliable paired pages in management data for the flash memory.